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PDF NB2305A Data sheet ( Hoja de datos )
| Número de pieza | NB2305A | |
| Descripción | Zero Delay Clock Buffer | |
| Fabricantes | ON Semiconductor | |
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NB2305A
3.3 V Zero Delay
Clock Buffer
The NB2305A is a versatile, 3.3 V zero delay buffer designed to
distribute high−speed clocks. It accepts one reference input and drives
out five low−skew clocks. It is available in a 8 pin package.
The −1H version of the NB2305A operates at up to 133 MHz, and
has higher drive than the −1 devices. All parts have on−chip PLL’s that
lock to an input clock on the REF pin. The PLL feedback is on−chip
and is obtained from the CLKOUT pad.
Multiple NB2305A devices can accept the same input clock and
distribute it. In this case the skew between the outputs of the two
devices is guaranteed to be less than 700 ps.
All outputs have less than 200 ps of cycle−to−cycle jitter. The input
and output propagation delay is guaranteed to be less than 350 ps, and
the output to output skew is guaranteed to be less than 250 ps.
The NB2305A is available in two different configurations, as shown
in the ordering information table. The NB2305A1 is the base part. The
NB2305Ax1H* is the high drive version of the −1 and its rise and fall
times are much faster than −1 part.
Features
• 15 MHz to 133 MHz Operating Range, Compatible with CPU and
PCI Bus Frequencies
• Zero Input − Output Propagation Delay
• Multiple Low−Skew Outputs
• Output−Output Skew Less than 250 ps
• Device−Device Skew Less than 700 ps
• One Input Drives 5 Outputs
• Less than 200 ps Cycle−to−Cycle Jitter is Compatible with PentiumR
Based Systems
• Available in 8 Pin, 150 mil SOIC Package and 8 Pin TSSOP 4.4 mm
• 3.3 V Operation, Advanced 0.35 m CMOS Technology
• These are Pb−Free Devices
http://onsemi.com
MARKING
DIAGRAMS*
8
1
SOIC−8
D SUFFIX
CASE 751
8
XXXX
ALYW
G
1
8
1
TSSOP−8
DT SUFFIX
CASE 948J
8
XXX
ALYWG
G
1
XXXX = Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*x = C for Commercial; I for Industrial.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 5
1
Publication Order Number:
NB2305A/D
1 page  
NB2305A
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the CLKOUT pin is
the internal feedback to the PLL, its relative loading can
adjust the input−output delay.
For applications requiring zero input−output delay, all
outputs, including CLKOUT, must be equally loaded. Even
if CLKOUT is not used, it must have a capacitive load equal
to that on other outputs, for obtaining zero−input−output
delay.
SWITCHING WAVEFORMS
1.4 V
t1
t2
1.4 V
1.4 V
Figure 3. Duty Cycle Timing
OUTPUT
2.0 V
0.8 V
t3
2.0 V
0.8 V
t4
3.3 V
0V
Figure 4. All Outputs Rise/Fall Time
OUTPUT
OUTPUT
1.4 V
t5
1.4 V
Figure 5. Output − Output Skew
INPUT
OUTPUT
VDD
2
t6
VDD
2
Figure 6. Input − Output Propagation Delay
CLKOUT, Device 1
CLKOUT, Device 2
VDD
2
VDD
2
t7
Figure 7. Device − Device Skew
http://onsemi.com
5
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet NB2305A.PDF ] | |
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