NB4L16M Datasheet PDF - ON Semiconductor
| Part Number | NB4L16M | |
| Description | Multi Level Clock/Data Input to CML Driver / Receiver / Buffer / Translator | |
| Manufacturers | ON Semiconductor | |
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NB4L16M
2.5V/3.3V, 5 Gb/s Multi Level
Clock/Data Input to CML
Driver / Receiver / Buffer/
Translator with Internal
Termination
Description
The NB4L16M is a differential driver/receiver/buffer/translator
which can accept LVPECL, LVDS, CML, HSTL, LVCMOS/LVTTL
and produce 400 mV CML output. The device is capable of receiving,
buffering, and translating a clock or data signal that is as small as
75 mV operating up to 3.5 GHz or 5.0 Gb/s, respectively. As such, it is
ideal for SONET, GigE, Fiber Channel and backplane applications
(see Table 6 and Figures 20, 21 22, and 23).
Differential inputs incorporate internal 50 W termination resistors
and accept LVPECL (Positive ECL), LVTTL/LVCMOS, CML, HSTL
or LVDS. The differential 16 mA CML output provides matching
internal 50 W termination, and 400 mV output swing when externally
receiver terminated, 50 W to VCC (see Figure 19). These features
provide transmission line termination on chip, at the receiver and
driver end, eliminating any use of additional external components.
The VBB, an internally generated voltage supply, is available to this
device only. For single−ended input configuration, the unused
complementary differential input is connected to VBB as a switching
reference voltage. The VBB reference output can be used also to
re−bias capacitor coupled differential or single−ended output signals.
For the capacitor coupled input signals, VBB should be connected to
the VTD pin and bypassed to ground with a 0.01 mF capacitor. When
not used VBB should be left open.
This device is housed in a 3x3 mm 16 pin QFN package.
Application notes, models, and support documentation are available at
www.onsemi.com.
Features
• Maximum Input Clock Frequency up to 3.5 GHz
• Maximum Input Data Rate up to 5.0 Gb/s
• < 0.7 ps Maximum Clock RMS Jitter
• < 10 ps Maximum Data Dependent Jitter at 2.5 Gb/s
• 220 ps Typical Propagation Delay
• 60 ps Typical Rise and Fall Times
• CML Output with Operating Range:
VCC = 2.375 V to 3.6 V with VEE = 0 V
• CML Output Level (400 mV Peak−to−Peak Output),
Differential Output Only
• 50 W Internal Input and Output Termination Resistors
• Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
• Pb−Free Packages are Available
http://onsemi.com
1
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB4L
16M
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VCC
VTD
50 W
D
D
50 W
VTD
R1
R2
R2
R1
Q
Q
VEE
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
February, 2006 − Rev. 1
1
Publication Order Number:
NB4L16M/D
|
| |
 
NB4L16M
Table 5. AC CHARACTERISTICS VCC = 2.375 V to 3.8 V, VEE = 0 V; (Note 8)
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
VOUTPP Output Voltage Amplitude (@VINPPmin) fin ≤ 3.5 GHz 280 400
(Figures 3 and 4)
fin ≤ 4.5 GHz 150 300
280 400
150 300
280 400
150 300
mV
fDATA
tPLH,
tPHL
Maximum Operating Data Rate
3.5 5.0
3.5 5.0
3.5 5.0
Gb/s
Propagation Delay to Output Differential @ 0.5 GHz 175 215 265 175 220 265 175 225 265
(Figure 6)
ps
tSKEW
Duty Cycle Skew (Note 9)
Device−to−Device Skew (Note 13)
2.0 10
6.0 90
2.0 10
6.0 90
2.0 10
6.0 90
ps
tJITTER RMS Random Clock Jitter (Note 11) fin ≤ 4.5 GHz
0.2 0.7
0.2 0.7
0.2 0.7 ps
VINPP
tr
tf
Peak−to−Peak Data Dependent Jitter
(Note 12)
fDATA = 2.5 Gb/s
fDATA = 3.5 Gb/s
fDATA = 5.0 Gb/s
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)
Output Rise/Fall Times @ 0.5 GHz
(Figure 5)
(20% − 80%)
75
1.5 10
2.0 12
9.0 25
VCC 75
−VEE
60 90
1.5 10
2.0 12
9.0 25
1.5 10
2.0 12
9.0 25
VCC 75 VCC
−VEE
−VEE
60 90
60 90
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured by forcing VINPP(MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps
(20% − 80%). See Figure 12 and 14.
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5 GHz.
10. VINPP(MAX) cannot exceed VCC − VEE. Input voltage swing is a single−ended measurement operating in differential mode. See Figure 11.
11. Additive RMS jitter with 50% duty cycle input clock signal.
12. Additive peak−to−peak data dependent jitter with NRZ input data signal, PRBS 223−1 and K28.7 pattern. See Figures 7, 8, 9, 10, 11 and 12.
13. Device−to−device skew is measured between outputs under identical transition @ 0.5 GHz.
http://onsemi.com
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