PDF ATR0630 Data sheet ( Hoja de datos )

Número de pieza	ATR0630
Descripción	Single-chip GPS Receiver
Fabricantes	ATMEL Corporation
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No Preview Available ! www.DataSheet4U.com Features • 16-channel GPS Correlator – 8192 Search Bins with GPS Acquisition Accelerator – Accuracy: 2.5m CEP (2D, Stand Alone) – Time to First Fix: 34s (Cold Start) – Acquisition Sensitivity: –139 dBm (With External LNA) – Tracking Sensitivity: –149 dBm (With External LNA) • Utilizes the ARM7TDMI® ARM® Thumb® Processor Core – High-performance 32-bit RISC Architecture – Embedded ICE (In-Circuit Emulation) • 128 Kbytes Internal RAM • 384 Kbytes Internal ROM with u-blox GPS Firmware • 1.5-bit ADC On-chip • Single IF Architecture • 2 External Interrupts • 24 User-programmable I/O Lines • 1 USB Device Port – Universal Serial Bus (USB) 2.0 Full-speed Device – Embedded USB V2.0 Full-speed Transceiver • 2 USARTs • Master/Slave SPI Interface – 4 External Slave Chip Selects • Programmable Watchdog Timer • Advanced Power Management Controller (APMC) – Geared Master Clock to Reduce Power Consumption – Sleep State with Disabled Master Clock – Hibernate State with 32.768 kHz Master Clock • Real Time Clock (RTC) • 1.8V to 3.3V User-definable IO Voltage for Several GPIOs with 5V Tolerance • 4 KBytes of Battery Backup Memory • 7 mm × 10 mm 96 Pin BGA Package, 0.8 mm Pitch, Pb-free, RoHS-compliant Benefits • Fully Integrated Design With Low BOM • No External Flash Memory Required • Requires Only a GPS XTAL, No TCXO • Supports NMEA, UBX Binary and RTCM Protocol • Supports SBAS (WAAS, EGNOS, MSAS) • Up to 4Hz Update Rate • Supports A-GPS (Aiding) • Excellent Noise Performance ANTARIS4 Single-chip GPS Receiver ATR0630 Preliminary Rev. 4920A–GPS–01/06 1 page www.DataSheet4U.com ATR0630 [Preliminary] 2.7 VGA/AGC The on-chip automatic gain control (AGC) stage sets the gain of the VGA in order to optimally load the input of the following analog-to-digital converter. The AGC control loop can be selected for on-chip closed-loop operation or for baseband controlled gain mode. 2.8 Analog-to-digital Converter The analog-to-digital converter stage has a total resolution of 1.5 bits. It comprises balanced comparators and a sub-sampling unit, clocked by the reference frequency (fXTO). The frequency spectrum of the digital output signal (fOUT), present at the data outputs SIGLO and SIGH1, is 4.348 MHz. 2.9 Baseband The GPS baseband core includes a 16-channel correlator and is based on an ARM7TDMI ARM processor core with very low power consumption. It has a high-performance 32 bit RISC archi- tecture, uses a high-density 16-bit instruction set, The ARM standard In-Circuit Emulation debug interface is supported via the JTAG/ICE port of the ATR0630. The ATR0630 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter- faces the processor with the on-chip 32-bit memories and the external memories and devices by means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip periph- erals and is optimized for low power consumption. The AMBA Bridge provides an interface between the ASB and the APB. An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip USARTs/SPI and the on- and off-chip memories without processor intervention. Most importantly, the PDC2 removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without reprogramming the starting address. As a result, the performance of the microcontroller is increased and the power consumption reduced. All of the external signals of the on-chip peripherals are under the control of the Parallel I/O Con- troller (PIO2). The PIO2 Controller can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. After reset, the user must carefully program the PIO2 Controller in order to define which peripheral signals are connected with off-chip logic. The ATR0630 features a Programmable Watchdog Timer. An Advanced Power Management Controller (APMC) allows for the peripherals to be deacti- vated individually. Automatic master clock gearing reduces power consumption. A Sleep Mode is available with disabled 23.104 MHz master clock, as well as a Back-up Mode operating 32.768 kHz master clock. A 32.768 kHz Real Time Clock (RTC), together with a buit-in battery back-up SRAM, allows for storage of Almanac, Ephemeris, software configurations to make quick hot- and warm starts. The ATR0630 includes full GPS firmware, licensed from u-blox AG, Switzerland. Features of the ROM firmware are described in software documentation available from u-blox AG, Switzerland. 4920A–GPS–01/06 5 5 Page www.DataSheet4U.com ATR0630 [Preliminary] Table 3-2. Signal Description (Continued) Pin Number Pin Name Type Active Level Pin Description/Comment Active Antenna Supervision C8 NANTSHORT DIGITAL IN Low Active antenna short detection Input G5, G6 NAADET0/NAA DET1 DIGITAL IN Low Active antenna detection Input F11 ANTON DIGITAL OUT - Active antenna power-on Output JTAG Interface E8 DBG_EN DIGITAL IN - Debug enable F9 TDO DIGITAL OUT - Test data out G9 TCK DIGITAL IN - Test clock G10 TMS DIGITAL IN - Test mode select H10 TDI DIGITAL IN - Test data in H11 NTRST DIGITAL IN Low Test reset input Debug/Test C3 MO ANALOG OUT - IF output buffer D3 TEST ANALOG IN - Enable IF output buffer B7 SIGLO DIGITAL OUT - Digital IF (data output “Low”) B8 SIGHI DIGITAL OUT - Digital IF (data output “High”) A8 CLK23 DIGITAL OUT - Digital IF (sample clock) Power Analog Part C2 VCC1 SUPPLY - Analog supply 3V E4 VCC2 SUPPLY - Analog supply 3V G2, G3, H2, H3 VBP SUPPLY - Analog supply 3V A3, B1, B4, D2, E[1-3], F[1-3], G1, H1 GNDA SUPPLY - Analog Ground Power Digital Part A5 VDIG SUPPLY - Digital supply (radio) 1.8V B9, E5, F12, G11,H9 VDD18 SUPPLY - Core voltage 1.8V A10 VDD_USB SUPPLY - USB transceiver supply voltage (3.0V to 3.6V (USB enabled) or 0 to 2.0V (USB disabled)) B5, H5 VDDIO SUPPLY - Variable I/O voltage 1.65V to 3.6V C5 GDIG SUPPLY - Digital ground (radio) A6, A9, B11, F5, H8, H12 GND SUPPLY - Digital ground LDO18 E11 LDO_IN SUPPLY - 2.3V to 3.6V E12 LDO_OUT SUPPLY - 1.8V LDO18 output, max. 80 mA LDOBAT D11 LDOBAT_IN SUPPLY - 2.3V to 3.6V D12 VBAT SUPPLY - 1.5V to 3.6V C12 VBAT18 SUPPLY - 1.8V LDOBAT Output 4920A–GPS–01/06 11 11 Page

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