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PDF AD8106 Data sheet ( Hoja de datos )
| Número de pieza | AD8106 | |
| Descripción | (AD8106 / AD8107) 16 x 5 Buffered Video Crosspoint Switches | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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1. AD8106  Hay una vista previa y un enlace de descarga de AD8106 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
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Data Sheet
FEATURES
16 × 5 high speed, nonblocking switch arrays
AD8106: G = 1
AD8107: G = 2
Pin compatible with AD8110/AD8111, 16 × 8 switch arrays
For a 16 × 16 array, see AD8114/AD8115
For a 16 x 8 array, see AD8110/AD8111
Complete solution
Buffered inputs
Five output amplifiers
Drives 150 Ω loads
Excellent video performance
60 MHz 0.1 dB gain flatness
0.02% differential gain error (RL = 150 Ω)
0.02° differential phase error (RL = 150 Ω)
Excellent ac performance
−3 dB bandwidth > 260 MHz
500 V/μs slew rate
Low power of 50 mA
Low all-hostile crosstalk of −78 dB at 5 MHz
Output disable allows connection of multiple device outputs
Reset pin allows disabling of all outputs
Excellent ESD rating: exceeds 4000 V human body model
80-lead LQFP (12 mm × 12 mm)
APPLICATIONS
Routing of high speed signals including:
Composite video (NTSC, PAL, S, SECAM)
Component video (YUV, RGB)
Compressed video (MPEG, Wavelet)
3-level digital video (HDB3)
GENERAL DESCRIPTION
The AD8106 and AD8107 are high speed, 16 × 5 video crosspoint
switch matrices. They offer a −3 dB signal bandwidth greater
than 260 MHz, and channel switch times of less than 25 ns
with 1% settling. With −78 dB of crosstalk and −97 dB isolation
(at 5 MHz), the AD8106/AD8107 are useful in many high speed
applications. The differential gain and differential phase of
greater than 0.02% and 0.02° respectively, along with 0.1 dB
flatness out to 60 MHz, make the AD8106/AD8107 ideal for
video signal switching.
260 MHz, 16 × 5 Buffered
Video Crosspoint Switches
AD8106/AD8107
FUNCTIONAL BLOCK DIAGRAM
D0 D1 D2 D3 D4
CLK
A0
A1
A2
25-BIT REGISTER
(RANK 1)
UPDATE
CE
RESET
25
PARALLEL LATCH
(RANK 2)
25
DECODE
5 × 5:16 DECODERS
SET INDIVIDUAL
OR RESET ALL
OUTPUTS
TO OFF
5
AD8106/AD8107
80
OUTPUT
BUFFER
G = 1,
G=2
16 INPUTS
SWITCH
MATRIX
5 OUTPUTS
Figure 1.
The AD8106 and AD8107 include five independent output
buffers that can be placed into a high impedance state for parallel-
ing crosspoint outputs, preventing off channels from loading the
output bus. The AD8106 has a gain of 1, while the AD8107
offers a gain of 2. Both operate on voltage supplies of ±5 V while
consuming only 30 mA of idle current. The channel switching is
performed via a parallel control, allowing updating of an individual
output without reprogramming the entire array.
The AD8106/AD8107 are offered in an 80-lead LQFP and are
available over the extended industrial temperature range of
−40°C to +85°C.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
TIMING CHARACTERISTICS
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
–
–
–
Limit at TMIN, TMAX
20
100
20
100
0
50
8
100
200
1
CLK
0
D0 TO D4 1
A0 TO A2
0
t2
t1 t3
1 = LATCHED
UPDATE
0 = TRANSPARENT
AD8106/AD8107
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
Description
Data setup time
CLK pulse width
Data hold time
CLK pulse separation
CLK to UPDATE delay
UPDATE pulse width
Propagation delay, UPDATE to switch on or off
CLK, UPDATE rise and fall times
RESET time
t4
Figure 2. Timing Diagram
t5 t6
Table 3. Logic Levels
VIH
RESET, CLK, D0, D1, D2, D3, D4,
A0, A1, A2, CE, UPDATE
2.0 V min
VIL
RESET, CLK, D0, D1, D2, D3, D4,
A0, A1, A2, CE, UPDATE
0.8 V max
IIH
RESET, CLK, D0, D1, D2, D3, D4,
A0, A1, A2, CE, UPDATE
20 µA max
IIL
RESET, CLK, D0, D1, D2, D3, D4,
A0, A1, A2, CE, UPDATE
−400 µA min
Rev. A | Page 5 of 22
5 Page 
Data Sheet
5
4
3
2
1
0
–1
–2
–3
100k
0.8
0.6
0.4
FLATNESS
GAIN
2V p-p
0.2
200mV p-p 0
–0.2
–0.4
–0.6
1M 10M 100M
FREQUENCY (Hz)
–0.8
1G
Figure 16. AD8107 Frequency Response
–20
RL = 1kΩ
–30
–40
–50
–60
–70
–80
–90
–100
–110
0.3
1
ADJACENT
ALL HOSTILE
10
FREQUENCY (MHz)
100 200
Figure 17. AD8107 Crosstalk vs. Frequency
–30
RL = 150Ω
–40 VOUT = 2V p-p
–50
–60
2ND HARMONIC
–70
3RD HARMONIC
–80
–90
–100
100k
1M 10M
FREQUENCY (Hz)
100M
Figure 18. AD8107 Distortion vs. Frequency
AD8106/AD8107
1.0
0.5
0
–0.5
–1.0
25ns/DIV
Figure 19. AD8107 Step Response, 100 mV Step
1.0
0.5
0
–0.5
–1.0
25ns/DIV
Figure 20. AD8107 Step Response, 2 V Step
2V STEP RTO
RL = 150Ω
0 10 20 30 40 50 60 70 80
10ns/DIV
Figure 21. AD8107 Settling Time
Rev. A | Page 11 of 22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet AD8106.PDF ] | |
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