AD9233 Datasheet PDF - Analog Devices
| Part Number | AD9233 | |
| Description | Analog-to-Digital Converter | |
| Manufacturers | Analog Devices | |
| Logo |  |
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12-Bit, 80 MSPS/105 MSPS/125 MSPS,
1.8 V Analog-to-Digital Converter
AD9233
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR = 69.5 dBc (70.5 dBFS) to 70 MHz input
SFDR = 85 dBc to 70 MHz input
Low power: 395 mW @ 125 MSPS
Differential input with 650 MHz bandwidth
On-chip voltage reference and sample-and-hold amplifier
DNL = ±0.15 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary, Gray code, or twos complement data format
Clock duty cycle stabilizer
Data output clock
Serial port control
Built-in selectable digital test pattern generation
Programmable clock and data alignment
APPLICATIONS
Ultrasound equipment
IF sampling in communications receivers
IS-95, CDMA-One, IMT-2000
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
GENERAL DESCRIPTION
The AD9233 is a monolithic, single 1.8 V supply, 12-bit, 80 MSPS/
105 MSPS/125 MSPS analog-to-digital converter (ADC), featuring
a high performance sample-and-hold amplifier (SHA) and on-
chip voltage reference. The product uses a multistage differential
pipeline architecture with output error correction logic to
provide 12-bit accuracy at 125 MSPS data rates and guarantees
no missing codes over the full operating temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets, including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
ADCs, the AD9233 is suitable for applications in communications,
imaging, and medical ultrasound.
A differential clock input controls all internal conversion cycles. A
duty cycle stabilizer (DCS) compensates for wide variations in the
clock duty cycle while maintaining excellent overall ADC
performance.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
VIN+
VIN–
REFT
REFB
VREF
SENSE
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
AD9233
SHA
MDAC1
8-STAGE
1 1/2-BIT PIPELINE
A/D
4
A/D
8
3
CORRECTION LOGIC
13
OUTPUT BUFFERS
REF
SELECT
0.5V
CLOCK
DUTY CYCLE
STABILIZER
MODE
SELECT
OR
DCO
D11 (MSB)
D0 (LSB)
SCLK/DFS
SDIO/DCS
CSB
AGND
CLK+ CLK–
Figure 1.
PDWN DRGND
The digital output data is presented in offset binary, Gray code, or
twos complement formats. A data output clock (DCO) is provided
to ensure proper latch timing with receiving logic.
The AD9233 is available in a 48-lead LFCSP and is specified
over the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9233 operates from a single 1.8 V power supply
and features a separate digital output driver supply to
accommodate 1.8 V to 3.3 V logic families.
2. The patented SHA input maintains excellent performance
for input frequencies up to 225 MHz.
3. The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
4. A standard serial port interface supports various product
features and functions, such as data formatting (offset
binary, twos complement, or Gray coding), enabling the
clock DCS, power-down, and voltage reference mode.
5. The AD9233 is pin compatible with the AD9246, allowing
a simple migration from 12 bits to 14 bits.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
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AD9233
AC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS enabled, unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
TWO-TONE SFDR
fIN = 30 MHz (−7 dBFS), 31 MHz (−7 dBFS)
fIN = 170 MHz (−7 dBFS), 171 MHz (−7 dBFS)
ANALOG INPUT BANDWIDTH
AD9233BCPZ-80
AD9233BCPZ-105 AD9233BCPZ-125
Temp Min Typ Max Min Typ Max Min Typ Max
25°C 69.5
25°C 69.5
Full 68.9
25°C 69.4
25°C 68.9
69.5
69.5
68.3
69.4
68.9
69.5
69.5
68.3
69.4
68.9
25°C 69.2
25°C 69.2
Full 68.5
25°C 69.1
25°C 68.6
69.2
69.2
67.3
69.1
68.6
69.2
69.2
67.3
69.1
68.6
25°C 11.4 11.4 11.4
25°C 11.4 11.4 11.4
25°C 11.4 11.4 11.4
25°C 11.3 11.3 11.3
25°C −90.0
−90.0
−90.0
25°C −85.0
−85.0
−85.0
Full
−76.0
−73.0
−73.0
25°C −85.0
−85.0
−85.0
25°C −83.5
−83.5
−83.5
25°C 90.0
25°C 85.0
Full 76.0
25°C 85.0
25°C 83.5
90.0
85.0
73.0
85.0
83.5
90.0
85.0
73.0
85.0
83.5
25°C −90.0
−90.0
−90.0
25°C −90.0
−90.0
−90.0
Full
−85.0
−81.0
−81.0
25°C −90.0
−90.0
−90.0
25°C −90.0
−90.0
−90.0
25°C 87 87 85
25°C 83 83 84
25°C 650 650 650
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBFS
MHz
1 See AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
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