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Siliconix - The FET Constant-Current Source/Limiter

Numéro de référence AN103
Description The FET Constant-Current Source/Limiter
Fabricant Siliconix 
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The FET Constant-Current Source/Limiter
AN103
Introduction
The combination of low associated operating voltage and
high output impedance makes the FET attractive as a
constant-current source. An adjustable-current source (Fig-
ure 1) may be built with a FET, a variable resistor, and a
small battery. For optimum thermal stability, the FET should
be biased near the zero temperature coefficient point.
D
S
RS
–+
RL
A change in supply voltage or a change in load imped-
ance, will change ID by only a small factor because of the
low output conductance goss.
DID = (DVDS)(goss)
(3)
The value of goss is an important consideration in the ac-
curacy of a constant-current source where the supply volt-
age may vary. As goss may range from less than 1 mS to
more than 50 mS according to the FET type, the dynamic
impedance can be greater than 1 MW to less than 20 kW.
This corresponds to a current stability range of 1 mA to
50 mA per volt. The value of goss also depends on the op-
erating point. Output conductance goss decrease approxi-
mately linearly with ID. The relationship is
ID
IDSS
+
goss
gȀoss
(4)
Figure 1. Field-Effect Transistor Current Source
NO TAG
where goss = gȀoss
(5)
Whenever the FET is operated in the current saturated re-
gion, its output conductance is very low. This occurs
whenever the drain-source voltage VDS is at least 50%
greater than the cut-off voltage VGS(off). The FET may be
biased to operate as a constant-current source at any cur-
rent below its saturation current IDSS.
Basic Source Biasing
For a given device where IDSS and VGS(off) are known, the
approximate VGS required for a given ID is
ƪ ǒ Ǔ ƫVGS + VGS(off)
1ńk
1–
ID
IDSS
(1)
where k can vary from 1.8 to 2.0, depending on device ge-
ometry. If K = 2.0, the series resistor RS required between
source and gate is
RS
+
VGS
ID
ǒ Ǹ Ǔor
RS
+
VGS(off)
ID
1–
ID
IDSS
(2)
when VGS = 0
(6)
So as VGS VGS(off), goss Zero. For best regulation,
ID must be considerably less than IDSS.
Cascading for Low goss
It is possible to achieve much lower goss per unit ID by
cascading two FETs, as shown in Figure 2.
D
Q1
S
SD
Q2
RS
–+
VDD
RL
Figure 2. Cascade FET Current Source
Updates to this app note may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70596.
Siliconix
10-Mar-97
1

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