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PDF K7A203200A Data sheet ( Hoja de datos )
| Número de pieza | K7A203200A | |
| Descripción | 64Kx32-Bit Synchronous Pipelined Burst SRAM | |
| Fabricantes | Samsung semiconductor | |
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K7A203200A
PRELIMINARY
64Kx32 Synchronous SRAM
Document Title
64Kx32-Bit Synchronous Pipelined Burst SRAM,
Revision History
Rev. No.
History
0.0 Final spec release.
1.0 Add VDDQ Supply voltage( 2.5V )
Draft Date
Nov. 10. 1998
Dec. 02. 1998
Remark
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - December 1998
Rev 1.0
1 page  
K7A203200A
PRELIMINARY
64Kx32 Synchronous SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1 CS2 CS2 ADSP ADSC ADV WRITE CLK
HXX
X
LXX ↑
LLX
L
XXX ↑
LXH
L
XXX ↑
LLX
X
LXX ↑
LXH
X
LXX ↑
LHL
L
XXX ↑
LHL
H
LXL ↑
LHL
H
LXH ↑
XXX
H
HLH ↑
HXX
X
HLH ↑
XXX
H
HLL ↑
HXX
X
HLL ↑
XXX
H
HHH ↑
HXX
X
HHH ↑
XXX
H
HHL ↑
HXX
X
HHL ↑
ADDRESS ACCESSED
N/A
N/A
N/A
N/A
N/A
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
Notes : 1. X means "Don′t Care".
2. The rising edge of clock is symbolized by ↑.
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE
GW
BW
WEa
WEb
WEc
WEd
HHXXXX
HL HHHH
HL L HHH
HL H L HH
HLHHL L
HL L LL L
LXXXXX
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
OPERATION
Not Selected
Not Selected
Not Selected
Not Selected
Not Selected
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
OPERATION
READ
READ
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c and d
WRITE ALL BYTEs
WRITE ALL BYTEs
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2):
OPERATION
ZZ OE I/O STATUS
Sleep Mode
HX
High-Z
Read
LL
LH
DQ
High-Z
Write
L X Din, High-Z
Deselected
LX
High-Z
Notes
1. X means "Don′t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must
be disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current
does not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
- 5 - December 1998
Rev 1.0
5 Page 
K7A203200A
PRELIMINARY
64Kx32 Synchronous SRAM
- 11 -
December 1998
Rev 1.0
11 Page | ||
| Páginas | Total 15 Páginas | |
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