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PDF CDB61577 Data sheet ( Hoja de datos )
| Número de pieza | CDB61577 | |
| Descripción | T1/E1 LINE INTERFACE | |
| Fabricantes | Cirrus Logic | |
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CS61577
T1/E1 Line Interface
Features
General Description
• Provides Analog Transmission Line
Interface for T1 and E1 Applications
• Drop-in Replacement for CS61574 with
the Following Enhancements:
- Lower Power Consumption
- Transmitter Short-Circuit
Current Limiting
- Greater Transmitter Immunity
to Line Reflections
The CS61577 is a drop-in replacement for the
CS61574, and combines the complete analog transmit
and receive line interface for T1 or E1 applications in a
low power, 28-pin device operating from a +5V supply.
The CS61577 supports processor-based or stand-
alone operation and interfaces with industry standard
T1 and E1 framers.
The receiver uses a digital Delay-Locked-Loop which is
continuously calibrated from a crystal reference to pro-
vide excellent stability and jitter tolerance. The receiver
includes a jitter attenuator optimized for minimum delay
in switching and transmission applications. The trans-
mitter provides internal pulse shaping to insure
compliance with T1 and E1 pulse template specifica-
tions.
Applications
- Software Selection Between 75Ω and
120Ω E1 Output Options
- Internally Controlled E1 Pulse Width
- B8ZS/HDB3/AMI Encoder/Decoder
• Interfacing Network Equipment such as DACS and
Channel Banks to a DSX-1 Cross Connect
• Building Channel Service Units
ORDERING INFORMATION
CS61577-IP1
28 Pin Plastic DIP
CS61577-IL1
28 Pin Plastic PLCC
( ) = Pin Function in Host Mode
[ ] = Pin Function in Extended Hardware Mode
(CLKE) (INT) (SDI) (SDO)
MODE TAOS LEN0 LEN1 LEN2 TGND
TV+
TCLK
TPOS
[TDATA]
2
3
4
TNEG
[TCODE]
8
RCLK
RPOS
[RDATA]
RNEG
[BPV]
7
6
AMI,
B8ZS,
HDB3,
CODER
R
E
M
O
T
E
L
O
O
P
B
A
C
K
JITTER
ATTENUATOR
26
9 10
1
RLOOP XTALIN XTALOUT ACLKI
(CS)
5 28 23 24 25
14 15
L
O
LINE DRIVER 13
C
A
CONTROL
PULSE
SHAPER
16
L
L LINE RECEIVER 19
O CLOCK &
O DATA
P RECOVERY
20
B 17
A SIGNAL
C
K
QUALITY
MONITOR
DRIVER
MONITOR
18
11
27 12
21
22
LLOOP
(SCLK)
LOS
RV+ RGND
TTIP
TRING
RTIP
RRING
MTIP
[RCODE]
MRING
[PCS]
DPM
[AIS]
Preliminary Product Information This document contains information for a new product. Crystal
Semiconductor reserves the right to modify this product without notice.
Crystal Semiconductor Corporation
P. O. Box 17847, Austin, Texas, 78760
(512) 445-7222 FAX:(512) 445-7581
Copyright © Crystal Semiconductor Corporation 1996
(All Rights Reserved)
MAY ’96
DS155PP2
1
1 page  
CS61577
T1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Symbol Min
Typ
Crystal Frequency
(Note 25)
fc
- 6.176000
TCLK Frequency
ftclk - 1.544
ACLKI Frequency
(Note 26) faclki
- 1.544
RCLK Duty Cycle
(Note 27) tpwh1/tpw1
45
50
Rise Time, All Digital Outputs
(Note 28)
tr
--
Fall Time, All Digital Outputs
(Note 28)
tf
--
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
tsu2 25
-
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
th2 25 -
RPOS/RNEG Valid Before RCLK Falling
(Note 29) tsu1
150 274
RDATA Valid Before RCLK Falling
(Note 30) tsu1
150 274
RPOS/RNEG Valid Before RCLK Rising
(Note 31) tsu1
150 274
RPOS/RNEG Valid After RCLK Falling
(Note 29)
th1
150 274
RDATA Valid After RCLK Falling
(Note 30)
th1
150 274
RPOS/RNEG Valid After RCLK Rising
(Note 31)
th1
150 274
Notes: 25. Crystal must meet specifications described in CXT6176/CXT8192 data sheet.
26. ACLKI provided by an external source or TCLK.
27. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator limits are reached.
28. At max load of 1.6 mA and 50 pF.
29. Host Mode (CLKE = 1).
30. Extended Hardware Mode.
31. Hardware Mode, or Host Mode (CLKE = 0)
32. The transmitted pulse width does not depend on the TCLK duty cycle.
Max
-
-
-
55
85
85
-
-
-
-
-
-
-
-
Units
MHz
MHz
MHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
E1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Crystal Frequency
(Note 25)
TCLK Frequency
TCLK Duty Cycle for LEN2/1/0 = 0/0/0
(Note 32)
ACLKI Frequency
RCLK Duty Cycle
(Note 26)
(Note 27)
Rise Time, All Digital Outputs
(Note 28)
Fall Time, All Digital Outputs
(Note 28)
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
RPOS/RNEG Valid Before RCLK Falling
RDATA Valid Before RCLK Falling
(Note 29)
(Note 30)
RPOS/RNEG Valid Before RCLK Rising
RPOS/RNEG Valid After RCLK Falling
(Note 31)
(Note 29)
RDATA Valid After RCLK Falling
RPOS/RNEG Valid After RCLK Rising
(Note 30)
(Note 31)
Symbol
fc
ftclk
tpwh2/tpw2
faclki
tpwh1/tpw1
tr
tf
tsu2
th2
tsu1
tsu1
tsu1
th1
th1
th1
Min Typ Max
- 8.192000 -
- 2.048 -
40 50 60
- 2.048 -
45 50 55
- - 85
- - 85
25 -
-
25 -
-
100 194
-
100 194
-
100 194
-
100 194
-
100 194
-
100 194
-
Units
MHz
MHz
%
MHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS155PP2
5
5 Page 
CS61577
Percent of
nominal
peak
voltage
120
110
100
90
80
269 ns
244 ns
194 ns
50
10 Nominal Pulse
0
-10
-20
219 ns
488 ns
Figure 9. Mask of the Pulse at the 2048 kbps Interface
Transmit All Ones Select
The transmitter provides for all ones insertion at
the frequency of TCLK. Transmit all ones is se-
lected when TAOS goes high, and causes
continuous ones to be transmitted on the line
(TTIP and TRING). In this mode, the TPOS and
TNEG (or TDATA) inputs are ignored. If Remote
Loopback is in effect, any TAOS request will be
ignored.
Receiver
The receiver extracts data and clock from an AMI
(Alternate Mark Inversion) coded signal and out-
puts clock and synchronized data. The receiver is
sensitive to signals over the entire range of
ABAM cable lengths and requires no equalization
or ALBO (Automatic Line Build Out) circuits.
The signal is received on both ends of a center-
tapped, center-grounded transformer. The
transformer is center tapped on the IC side. The
clock and data recovery circuit exceeds the jitter
tolerance specifications of Publications 43802,
43801, AT&T 62411, TR-TSY-000170, and
CCITT REC. G.823.
A block diagram of the receiver is shown in Fig-
ure 10. The two leads of the transformer (RTIP
and RRING) have opposite polarity allowing the
receiver to treat RTIP and RRING as unipolar sig-
nals. Comparators are used to detect pulses on
RTIP and RRING. The comparator thresholds are
dynamically established at a percent of the peak
level (50% of peak for E1, 65% of peak for T1;
with the slicing level selected by LEN2/1/0 in-
puts).
The leading edge of an incoming data pulse trig-
gers the clock phase selector. The phase selector
chooses one of the 13 available phases which the
delay line produces for each bit period. The out-
For c oax ia l c able, For shielded twisted
75Ω loa d a nd pair, 120Ω load and
transformer specified transformer specified
in Application Section. in Application Section.
Nominal peak voltage of a mark (pulse)
2.37 V
3V
Peak voltage of a space (no pulse)
0 ±0.237 V
0 ±0.30 V
Nominal pulse width
244 ns
Ratio of the amplitudes of positive and negative
pulses at the center of the pulse interval
0.95 to 1.05*
Ratio of the widths of positive and negative
pulses at the nominal half amplitude
0.95 to 1.05*
* When configured with a 0.47 µF nonpolarized capacitor in series with the TX transformer
primary as shown in Figures A1, A2 and A3.
Table 4. CCITT G.703 Specifications
DS155PP2
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CDB61577.PDF ] | |
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