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Lucent - (ATT3000 Series) Field-Programmable Gate Arrays

Numéro de référence ATT3020
Description (ATT3000 Series) Field-Programmable Gate Arrays
Fabricant Lucent 
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ATT3020 fiche technique
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Features
s High performance:
— Up to 270 MHz toggle rates
— 4-input LUT delays <2.7 ns
s User-programmable gate arrays
— Unlimited reprogrammability
— Easy design iteration through in-system
logic changes
s Flexible array architecture:
— Compatible arrays ranging from 1500 to
6000 gate logic complexity
— Extensive register, combinatorial, and I/O
capabilities
— Low-skew clock nets
— High fan-out signal distribution
— Internal 3-state bus capabilities
— TTL or CMOS input thresholds
— On-chip oscillator amplifier
s Standard product availability:
— Low-power 0.55 µm CMOS, static memory
technology
— Pin-for-pin compatible with Xilinx* XC3000*
and XC3100* families
— Cost-effective for volume production
— 100% factory pretested
— Selectable configuration modes
s ORCAFoundry for ATT3000 Development
System support
s All FPGAs processed on a QML-certified line
s Extensive packaging options
Description
The CMOS ATT3000 Series Field-Programmable
Gate Array (FPGA) family provides a group of high-
density, digital integrated circuits. Their regular,
extendable, flexible, user-programmable array
architecture is composed of a configuration program
store plus three types of configurable elements: a
perimeter of I/O blocks, a core array of logic blocks,
and resources for interconnection. The general struc-
ture of an FPGA is shown in Figure 1.
The ORCA Foundry for ATT3000 Development Sys-
tem provides automatic place and route of netlists.
Logic and timing simulation are available as design
verification alternatives. The design editor is used for
interactive design optimization and to compile the
data pattern that represents the configuration pro-
gram.
The FPGA’s user-logic functions and interconnec-
tions are determined by the configuration program
data stored in internal static memory cells. The pro-
gram can be loaded in any of several modes to
accommodate various system requirements. The
program data resides externally in an EEPROM,
EPROM, or ROM on the application circuit board, or
on a floppy disk or hard disk. On-chip initialization
logic provides for optional automatic loading of pro-
gram data at powerup. A serial configuration PROM
can provide a very simple serial configuration pro-
gram storage.
* Xilinx, XC3000, and XC3100 are registered trademarks of
Xilinx, Inc.
Table 1. ATT3000 Series FPGAs
FPGA
ATT3020
ATT3030
ATT3042
ATT3064
ATT3090
Max
Logic
Gates
1,500
2,000
3,000
4,500
6,000
Typical Gate
Range
1,000—1,500
1,500—2,000
2,000—3,000
3,500—4,500
5,000—6,000
Configurable
Logic
Blocks
64
100
144
224
320
Array
8x8
10 x 10
12 x 12
16 x 14
20 x 16
User I/Os
Max
64
80
96
120
144
Flip-
Flops
256
360
480
688
928
Horizontal Configuration
Long Lines Data Bits
16 14,779
20 22,176
24 30,784
32 46,064
40 64,160

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