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PDF ATT3064 Data sheet ( Hoja de datos )
| Número de pieza | ATT3064 | |
| Descripción | (ATT3000 Series) Field-Programmable Gate Arrays | |
| Fabricantes | Lucent | |
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Features
s High performance:
— Up to 270 MHz toggle rates
— 4-input LUT delays <2.7 ns
s User-programmable gate arrays
— Unlimited reprogrammability
— Easy design iteration through in-system
logic changes
s Flexible array architecture:
— Compatible arrays ranging from 1500 to
6000 gate logic complexity
— Extensive register, combinatorial, and I/O
capabilities
— Low-skew clock nets
— High fan-out signal distribution
— Internal 3-state bus capabilities
— TTL or CMOS input thresholds
— On-chip oscillator amplifier
s Standard product availability:
— Low-power 0.55 µm CMOS, static memory
technology
— Pin-for-pin compatible with Xilinx* XC3000*
and XC3100* families
— Cost-effective for volume production
— 100% factory pretested
— Selectable configuration modes
s ORCA™ Foundry for ATT3000 Development
System support
s All FPGAs processed on a QML-certified line
s Extensive packaging options
Description
The CMOS ATT3000 Series Field-Programmable
Gate Array (FPGA) family provides a group of high-
density, digital integrated circuits. Their regular,
extendable, flexible, user-programmable array
architecture is composed of a configuration program
store plus three types of configurable elements: a
perimeter of I/O blocks, a core array of logic blocks,
and resources for interconnection. The general struc-
ture of an FPGA is shown in Figure 1.
The ORCA Foundry for ATT3000 Development Sys-
tem provides automatic place and route of netlists.
Logic and timing simulation are available as design
verification alternatives. The design editor is used for
interactive design optimization and to compile the
data pattern that represents the configuration pro-
gram.
The FPGA’s user-logic functions and interconnec-
tions are determined by the configuration program
data stored in internal static memory cells. The pro-
gram can be loaded in any of several modes to
accommodate various system requirements. The
program data resides externally in an EEPROM,
EPROM, or ROM on the application circuit board, or
on a floppy disk or hard disk. On-chip initialization
logic provides for optional automatic loading of pro-
gram data at powerup. A serial configuration PROM
can provide a very simple serial configuration pro-
gram storage.
* Xilinx, XC3000, and XC3100 are registered trademarks of
Xilinx, Inc.
Table 1. ATT3000 Series FPGAs
FPGA
ATT3020
ATT3030
ATT3042
ATT3064
ATT3090
Max
Logic
Gates
1,500
2,000
3,000
4,500
6,000
Typical Gate
Range
1,000—1,500
1,500—2,000
2,000—3,000
3,500—4,500
5,000—6,000
Configurable
Logic
Blocks
64
100
144
224
320
Array
8x8
10 x 10
12 x 12
16 x 14
20 x 16
User I/Os
Max
64
80
96
120
144
Flip-
Flops
256
360
480
688
928
Horizontal Configuration
Long Lines Data Bits
16 14,779
20 22,176
24 30,784
32 46,064
40 64,160
1 page  
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
I/O Block
Each user-configurable I/O block (IOB), shown in
Figure 3, provides an interface between the external
package pin of the device and the internal user logic.
Each IOB includes both registered and direct input
paths and a programmable 3-state output buffer which
may be driven by a registered or direct output signal.
Configuration options allow each IOB an inversion, a
controlled slew rate, and a high-impedance pull-up.
Each input circuit also provides input clamping diodes
to provide electrostatic protection and circuits to inhibit
latch-up produced by input currents.
The input buffer portion of each IOB provides threshold
detection to translate external signals applied to the
package pin to internal logic levels. The global input-
buffer threshold of the IOB can be programmed to be
compatible with either TTL or CMOS levels. The buff-
ered input signal drives the data input of a storage
element which may be configured as a positive-edge
triggered D flip-flop or a low-level transparent latch. The
sense of the clock can be inverted (negative edge/high
transparent) as long as all IOBs on the same clock net
use the same clock sense. Clock/load signals (IOB pins
.ik and .ok) can be selected from either of two die edge
metal lines. I/O storage elements are reset during con-
figuration or by the active-low chip RESET input. Both
direct input (from IOB pin .i) and registered input (from
IOB pin .q) signals are available for interconnect.
PROGRAM-CONTROLLED MEMORY CELLS
VCC
OUT
INVERT
3-STATE
INVERT
OUTPUT
SELECT
SLEW
RATE
PASSIVE
PULL UP
3-STATE
OUTPUT ENABLE
OUT
.t
.o
DIRECT IN
REGISTERED IN
.i
.q
DQ
FLIP-
FLOP
R
OUTPUT
BUFFER
I/O PAD
QD
FLIP-
FLOP
OR
LATCH
R
TTL OR
CMOS
INPUT
THRESHOLD
.ok .lk
(GLOBAL RESET)
CK1
PROGRAM-
CONTROLLED
MULTIPLEXER
CK2
= PROGRAMMABLE INTERCONNECTION POINT OR PIP
Figure 3. Input/Output Block
5-3102(F)
Lucent Technologies Inc.
5
5 Page 
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Programmable Interconnect (continued)
Direct Interconnect
Direct interconnect (shown in Figure 11) provides the
most efficient implementation of networks between
adjacent logic or IOBs. Signals routed from block to
block using the direct interconnect exhibit minimum
interconnect propagation and use no general intercon-
nect resources. For each CLB, the .x output may be
connected directly to the .b input of the CLB immedi-
ately to its right and to the .c input of the CLB to its left.
The .y output can use direct interconnect to drive the .d
input of the block immediately above, and the .a input
of the block below. Direct interconnect should be used
to maximize the speed of high-performance portions of
logic. Where logic blocks are adjacent to IOBs, direct
connect is provided alternately to the IOB inputs (.i)
and outputs (.o) on all four edges of the die. The right
edge provides additional direct connects from CLB out-
puts to adjacent IOBs. Direct interconnections of IOBs
with CLBs are shown in Figure 12.
Figure 11. Direct Interconnect
Lucent Technologies Inc.
11
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