CDB61581 Datasheet PDF - Cirrus Logic
| Part Number | CDB61581 | |
| Description | Universal Line Interface Unit | |
| Manufacturers | Cirrus Logic | |
| Logo |  |
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CDB61581
Universal Line Interface Unit
Features
s Socketed CS61581 Universal Line Interface
s All Required Components for CS61581 Evaluation
s LED Status Indications for Alarm Conditions and
Operating Status
s Support for Hardware and Host Modes
Description
The evaluation board includes a socketed CS61581 line
interface device and all support components necessary
for evaluation. The board is powered by an external
+5 Volt supply.
The board may be configured for 100 Ω twisted-pair T1,
75 Ω coax E1, or 120 Ω twisted-pair E1 short and long
haul operations. Binding posts and bantam jacks are
provided for the line interface connections. Several
BNC connectors provide clock and data I/O at the sys-
tem interface. Reference timing may be derived from a
quartz crystal or an external reference clock. Four LED
indicators monitor device alarm conditions and operat-
ing status.
ORDERING INFO:
CDB61581
5V+ 0V
TCLK
TPOS
TNEG
RCLK
RPOS
RNEG
Hardware Control
and Mode Circuit
LED Status
Indicators
Serial Interface
Control Circuit
TTIP
TRING
RTIP
CS61581
XTALIN
RRING
MCLK
+5V
4.7 kΩ
XTL (optional)
XTALOUT
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 1999
(All Rights Reserved)
OCT ‘99
DS211DB2
1
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CDB61581
6. LED INDICATORS
The four-LED pack D1 indicates signal states on
LATN1, LATN2, LOS and NLOOP. The LOS
LED indicator illuminates when the line interface
receiver has detected a loss of signal. The NLOOP
LED indicates if Network Loopback is in opera-
tion. The LATN1/LATN2 LED’s indicate the at-
tenuation level of the received signal; reading how
much the incoming signal is below the nominal ex-
pected signal level. See Table 1 for details.
7. BUFFERING
Buffer U2 provides additional drive capability for
the SW1 and Host mode connections. The buffer
outputs are filtered with an (optional) RC network
(not initially populated) to reduce the transients
caused by buffer switching.
8. TRANSFORMER SELECTION
The evaluation board is supplied from the factory
with PE-64936 (1:1), PE-65351 (1:2) and T-1054
(1:1.5) transformers by Pulse Engineering. The
socket T1 on the board is for receive side trans-
former and T2 is for the transmit side. In the
matched impedance mode HDR1-HDR2 should be
placed in the MATZ positions, and in the low im-
pedance mode in the LOWZ positions. Please see
Table 2 for details on transformers selection.
9. PROTOTYPING AREA
An ample prototyping area with power supply and
ground connections is provided on the evaluation
board. This area can be used to develop and test a
variety of additional circuits such as framer devic-
es, system synchronizer PLLs, or specialized inter-
face logic.
LATN1
ON
OFF
ON
OFF
LATN2
ON
OFF
OFF
ON
Attenuation Level (dB)
0
7.5
15
22.5
Table 1. LATN Settings
Mode
T1 (100 Ω)/LH/Low Z*
E1 (120 Ω)/LH/Low Z
T1 (100 Ω)/SH/Mat Z
E1 (75 Ω)/SH/Mat Z
E1 (120 Ω)/SH/Mat Z
TX Transformer
1:2
1:2
1:1.5
1:1.5
1:1.5
RX Transformer
1:1
1:1
1:1
1:1
1:1
R1-R2
50 Ω
60 Ω
50 Ω
37.5 Ω
60 Ω
R3-R4
12.5 Ω
15 Ω
0**
0**
0**
Table 2. Transformer and Resistor Options
SH=Short Haul; LH = Long Haul; Mat Z = Matched Impedance; Low Z = Low Impedance
* Default setting from the factory; **R3-R4 are shorted by placing HDR1-HDR2 in MATZ positions.
DS211DB2
5
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| Information | Total 16 Pages | |
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