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PDF ISL12026 Data sheet ( Hoja de datos )
| Número de pieza | ISL12026 | |
| Descripción | Real Time Clock/Calendar | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
ISL12026, ISL12026A
November 30, 2010
FN8231.9
Real Time Clock/Calendar with I2C Bus™
and EEPROM
The ISL12026 and the ISL12026A devices are micro power
real time clocks with timing and crystal compensation,
clock/calender, power-fail indicator, two periodic or polled
alarms, intelligent battery backup switching, and integrated
512x8-bit EEPROM configured in 16 Bytes per page.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
The ISL12026 and ISL12026A have different types of Power
Control Settings. The ISL12026 uses the Legacy Mode
Setting, which follows conditions set in X1226 products. The
ISL12026A uses the Standard Mode Setting. Please refer to
“Power Control Operation” on page 13 for more details. Also,
please refer to “I2C Communications During Battery Backup”
on page 22 for important details.
Pinouts
ISL12026, ISL12026A
(8 LD SOIC)
TOP VIEW
X1
X2
IRQ/FOUT
GND
1
2
3
4
8 VDD
7 VBAT
6 SCL
5 SDA
ISL12026, ISL12026A
(8 LD TSSOP)
TOP VIEW
VBAT
VDD
X1
X2
1
2
3
4
8 SCL
7 SDA
6 GND
5 IRQ/FOUT
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
- 3 Selectable Frequency Outputs
• Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day or Month
- Repeat Mode (Periodic Interrupts)
• Automatic Backup to Battery or SuperCap
• On-Chip Oscillator Compensation
- Internal Feedback Resistor and Compensation
Capacitors
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
• 512x8 Bits of EEPROM
- 16-Byte Page Write Mode (32 total pages)
- 8 Modes of BlockLock™ Protection
- Single Byte Write Capability
• High Reliability
- Data Retention: 50 years
- Endurance: >2,000,000 Cycles Per Byte
• I2C Interface
- 400kHz Data Transfer Rate
• 800nA Battery Supply Current
• Package Options
- 8 Ld SOIC and 8 Ld TSSOP Packages
• Pb-Free (RoHS Compliant)
Applications
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Set-Top Box/Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2005, 2006, 2007, 2008, 2010. All Rights Reserved.
Intersil (and design) and BlockLock are trademarks owned by Intersil Corporation or one of its subsidiaries.
I2C Bus™ is a trademark owned by NXP Semiconductors Netherlands, B.V. All other trademarks mentioned are the property of their respective owners.
1 page  
ISL12026, ISL12026A
AC Electrical Specifications (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 16)
MAX
TYP (Note 16) UNITS NOTES
tSU:STO STOP Condition Set-up Time
tHD:STO
tDH
STOP Condition Hold Time for
Read or Volatile Only Write
Output Data Hold Time
Cpin SDA and SCL Pin Capacitance
From SCL rising edge crossing 70%
of VDD, to SDA rising edge crossing
30% of VDD.
From SDA rising edge to SCL falling
edge. Both crossing 70% of VDD.
From SCL falling edge crossing 30%
of VDD, until SDA enters the 30% to
70% of VDD window.
600
600
0
ns
ns
ns
10 pF
tWC Non-volatile Write Cycle Time
tR SDA and SCL Rise Time
From 30% to 70% of VDD
tF SDA and SCL Fall Time
From 70% to 30% of VDD
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip
12 20 ms
20 + 0.1xCb
300 ns
20 +0.1xCb
300 ns
10 400 pF
14
15
15
RPU SDA and SCL Bus Pull-up Resistor Maximum is determined by tR and tF.
Off-chip
For Cb = 400pF, max is about
2kΩ~2.5kΩ.
For Cb = 40pF, max is about
15kΩ~20kΩ
1
kΩ 15
NOTES:
7. IRQ/FOUT Inactive.
8. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz
9. VDD > VBAT +VBATHYS
10. Bit BSW = 0 (Standard Mode), ATR = 00h, VBAT ≥1.8V
11. Specified at +25°C.
12. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
13. Parameter is not 100% tested.
14. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
15. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
16. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Timing Diagrams
Bus Timing
SCL
tSU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tF tHIGH
tSU:DAT
tHD:STA
tLOW
tR
tHD:DAT
tAA tDH
tHD:STO
tSU:STO
tBUF
5 FN8231.9
November 30, 2010
5 Page 
ISL12026, ISL12026A
TABLE 3.
PROTECTED ADDRESSES
ISL12026
ARRAY LOCK
000
None (Default)
None
001
010
011
100
101
110
111
180h – 1FFh
100h – 1FFh
000h – 1FFh
000h – 03Fh
000h – 07Fh
000h – 0FFh
000h – 1FFh
Upper 1/4
Upper 1/2
Full Array
First 4 Pages
First 8 Pages
First 16 Pages
Full Array
INT Register: Interrupt Control and
Frequency Output Register
IM, AL1E, AL0E - Interrupt Control and Status Bits
There are two Interrupt Control bits, Alarm 1 Interrupt Enable
(AL1E) and Alarm 0 Interrupt Enable (AL0E) to specifically
enable or disable the alarm interrupt signal output
(IRQ/FOUT). The interrupts are enabled when either the
AL1E or AL0E or both bits are set to ‘1’ and both the FO1
and FO0 bits are set to 0 (FOUT disabled).
The IM bit enables the pulsed interrupt mode. To enter this
mode, the AL0E or AL1E bits are set to “1”, and the IM bit to
“1”. The IRQ/FOUT output will now be pulsed each time an
alarm occurs. This means that once the interrupt mode alarm
is set, it will continue to alarm for each occurring match of the
alarm and present time. This mode is convenient for hourly or
daily hardware interrupts in microcontroller applications such
as security cameras or utility meter reading.
In the case that both Alarm 0 and Alarm 1 are enabled, the
IRQ/FOUT pin will be pulsed each time either alarm matches
the RTC (both alarms can provide hardware interrupt). If the
IM bit is also set to "1", the IRQ/FOUT will be pulsed for each
of the alarms as well.
FO1, FO0 - Programmable Frequency Output Bits
These are two output control bits. They select one of three
divisions of the internal oscillator, that is applied to the
IRQ/FOUT output pin. Table 4 shows the selection bits for
this output. When using this function, the Alarm output
function is disabled.
TABLE 4. PROGRAMMABLE FREQUENCY OUTPUT BITS
FO1 FO0
OUTPUT FREQUENCY
00
01
10
11
Alarm output (FOUT disabled)
32.768kHz
4096Hz
1Hz
Oscillator Compensation Registers
There are two trimming options.
• ATR. Analog Trimming Register
• DTR. Digital Trimming Register
These registers are non-volatile. The combination of analog
and digital trimming can give up to -64 to +110 ppm of total
adjustment.
ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1,
ATR0: Analog Trimming Register
6 analog trimming bits, ATR0 to ATR5, are provided in order
to adjust the on-chip load capacitance value for frequency
compensation of the RTC. Each bit has a different weight for
capacitance adjustment. For example, using a Citizen CFS-
206 crystal with different ATR bit combinations provides an
estimated ppm adjustment range from -34 to +80ppm to the
nominal frequency compensation.
X1
CX1
X2
CX2
CRYSTAL
OSCILLATOR
FIGURE 8. DIAGRAM OF ATR
The effective on-chip series load capacitance, CLOAD,
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). CLOAD is changed via two digitally
controlled capacitors, CX1 and CX2, connected from the X1
and X2 pins to ground (see Figure 8). The value of CX1 and
CX2 is given by Equation 1:
CX = (16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9)pF
(EQ. 1)
The effective series load capacitance is the combination of
CX1 and CX2:
CLOAD
=
----------------1------------------
⎛
⎝
-----1-----
CX1
+
C-----1X----2-⎠⎞
CLOAD
=
⎛
⎝
-1--6-----⋅---b---5----+-----8----⋅---b---4-----+----4----⋅---b----3----+----2-2----⋅---b---2----+----1-----⋅---b---1----+-----0---.-5----⋅----b---0----+----9--⎠⎞
p
F
(EQ. 2)
For example, CLOAD(ATR = 00000) = 12.5pF, CLOAD
(ATR = 100000) = 4.5pF, and CLOAD(ATR = 011111) = 20.25pF.
The entire range for the series combination of load capacitance
goes from 4.5pF to 20.25pF in 0.25pF steps. Note that these
are typical values.
11 FN8231.9
November 30, 2010
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ISL12026.PDF ] | |
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