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PDF PZ3064 Data sheet ( Hoja de datos )
| Número de pieza | PZ3064 | |
| Descripción | 64 macrocell CPLD | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
PZ3064
64 macrocell CPLD
Product specification
IC27 Data Handbook
Philips
Semiconductors
1997 Mar 05
1 page  
Philips Semiconductors
64 macrocell CPLD
Product specification
PZ3064
Macrocell Architecture
Figure 3 shows the architecture of the macrocell used in the
CoolRunner™ family. The macrocell consists of a flip-flop that can be
configured as either a D or T type. A D-type flip-flop is generally
more useful for implementing state machines and data buffering. A
T-type flip-flop is generally more useful in implementing counters. All
CoolRunner™ family members provide both synchronous and
asynchronous clocking and provide the ability to clock off either the
falling or rising edges of these clocks. These devices are designed
such that the skew between the rising and falling edges of a clock
are minimized for clocking integrity. There are 4 clocks available on
the PZ3064 device. Clock 0 (CLK0) is designated as the
“synchronous” clock and must be driven by an external source.
Clock 1 (CLK1), Clock 2 (CLK2), and Clock 3 (CLK3) can either be
used as a synchronous clock (driven by an external source) or as an
asynchronous clock (driven by a macrocell equation).
Two of the control terms (CT0 and CT1) are used to control the
Preset/Reset of the macrocell’s flip-flop. The Preset/Reset feature
for each macrocell can also be disabled. Note that the Power-on
Reset leaves all macrocells in the “zero” state when power is
properly applied. The other 4 control terms (CT2–CT5) can be used
to control the Output Enable of the macrocell’s output buffers. The
reason there are as many control terms dedicated for the Output
Enable of the macrocell is to insure that all CoolRunner™ devices
are PCI compliant. The macrocell’s output buffers can also be
always enabled or disabled. All CoolRunner™ devices also provide a
Global Tri-State (GTS) pin, which, when pulled Low, will 3-State all
the outputs of the device. This pin is provided to support “In-Circuit
Testing” or “Bed-of-Nails Testing”.
There are two feedback paths to the ZIA: one from the macrocell,
and one from the I/O pin. The ZIA feedback path before the output
buffer is the macrocell feedback path, while the ZIA feedback path
after the output buffer is the I/O pin ZIA path. When the macrocell is
used as an output, the output buffer is enabled, and the macrocell
feedback path can be used to feedback the logic implemented in the
macrocell. When the I/O pin is used as an input, the output buffer
will be 3-Stated and the input signal will be fed into the ZIA via the
I/O feedback path, and the logic implemented in the buried
macrocell can be fed back to the ZIA via the macrocell feedback
path. It should be noted that unused inputs or I/Os should be
properly terminated.
TO ZIA
CLK0
CLK0
CLK1
CLK1
CLK2
CLK2
CLK3
CLK3
D/T Q
INIT
(P or R)
GTS
CT0
CT1
GND
CT2
CT3
CT4
CT5
VCC
GND
Figure 3. PZ3064 Macrocell Architecture
GND
SP00457
1997 Mar 05
85
5 Page 
Philips Semiconductors
64 macrocell CPLD
Product specification
PZ3064
PIN DESCRIPTIONS
PZ3064 – 44-Pin Plastic Leaded Chip Carrier
6 1 40
7 39
LCC
17 29
18 28
Pin Function
1 IN1
2 IN3
3 VDD
4 I/O-A0/CK3
5 I/O-A2
6 I/O-A5
7 I/O-A8 (TDI)
8 I/O-A11
9 I/O-A12
10 GND
11 I/O-A13
12 I/O-A15
13 I/O-B15 (TMS)*
14 I/O-B13
15 VDD
Pin Function
16 I/O-B10
17 I/O-B8
18 I/O-B4
19 I/O-B3
20 I/O-B2
21 I/O-B0/CK2
22 GND
23 VDD
24 I/O-C0/CK1
25 I/O-C2
26 I/O-C3
27 I/O-C4
28 I/O-C7
29 I/O-C8
30 GND
* THE TEST MODE SELECT (TMS) FUNCTION IS
INACTIVE ON NON-ISR ARCHITECTURES.
Pin Function
31 I/O-C13
32 I/O-C15 (TCK)
33 I/O-D15
34 I/O-D13
35 VDD
36 I/O-D12
37 I/O-D11
38 I/O-D8 (TDO)
39 I/O-D7
40 I/O-D2
41 I/O-D0
42 GND
43 IN0-CK0
44 IN2-gtsn
SP00452A
PZ3064 – 44-Pin Thin Quad Flat Package
44 34
1 33
QFP
11 23
12 22
Pin Function
1 I/O-A8
2 I/O-A11
3 I/O-A12
4 GND
5 I/O-A13
6 I/O-A15
7 I/O-B15 (TMS)*
8 I/O-B13
9 VDD
10 I/O-B10
11 I/O-B8
12 I/O-B4
13 I/O-B3
14 I/O-B2
15 I/O-B0/CK2
Pin Function
16 GND
17 VDD
18 I/O-C0/CK1
19 I/O-C2
20 I/O-C3
21 I/O-C4
22 I/O-C7
23 I/O-C8
24 GND
25 I/O-C13
26 I/O-C15 (TCK)
27 I/O-D15
28 I/O-D13
29 VDD
30 I/O-D12
Pin Function
31 I/O-D11
32 I/O-D8 (TDO)
33 I/O-D7
34 I/O-D2
35 I/O-D0
36 GND
37 IN0/CK0
38 IN2-gtsn
39 IN1
40 IN3
41 VDD
42 I/O-A0/CK3
43 I/O-A2
44 I/O-A5
* THE TEST MODE SELECT (TMS) FUNCTION IS
INACTIVE ON NON-ISR ARCHITECTURES.
SP00453
PZ3064 – 68-Pin Plastic Leaded Chip Carrier
91
61
10 60
LCC
26 44
27 43
Pin Function
1 IN1
2 IN3
3 VDD
4 I/O-A0/CK3
5 I/O-A2
6 GND
7 I/O-A3
8 I/O-A4
9 I/O-A5
10 I/O-A7
11 VDD
12 I/O-A8 (TDI)
13 I/O-A10
14 I/O-A11
15 I/O-A12
16 GND
17 I/O-A13
18 I/O-A15
19 I/O-B15 (TMS)*
20 I/O-B13
21 VDD
22 I/O-B12
23 I/O-B11
Pin Function
24 I/O-B10
25 I/O-B8
26 GND
27 I/O-B7
28 I/O-B5
29 I/O-B4
30 I/O-B3
31 VDD
32 I/O-B2
33 I/O-B0/CK2
34 GND
35 VDD
36 I/O-C0/CK1
37 I/O-C2
38 GND
39 I/O-C3
40 I/O-C4
41 I/O-C5
42 I/O-C7
43 VDD
44 I/O-C8
45 I/O-C10
46 I/O-C11
Pin Function
47 I/O-C12
48 GND
49 I/O-D13
50 I/O-C15 (TCK)
51 I/O-D15
52 I/O-D13
53 VDD
54 I/O-D12
55 I/O-D11
56 I/O-D9
57 I/O-D8 (TDO)
58 GND
59 I/O-D7
60 I/O-D6
61 I/O-D4
62 I/O-D3
63 VDD
64 I/O-D2
65 I/O-D0
66 GND
67 IN0/CK0
68 IN2-gtsn
* THE TEST MODE SELECT (TMS) FUNCTION IS
INACTIVE ON NON-ISR ARCHITECTURES.
SP00454
1997 Mar 05
91
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet PZ3064.PDF ] | |
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