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PDF A8499 Data sheet ( Hoja de datos )
| Número de pieza | A8499 | |
| Descripción | High Voltage Step-Down Regulator | |
| Fabricantes | Allegro MicroSystems | |
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Features and Benefits
▪ 8 to 50 V input range
▪ Integrated DMOS switch
▪ Adjustable fixed off-time
▪ Highly efficient
▪ Adjustable 1.2 to 24 V output
A8499
High Voltage Step-Down Regulator
Description
The A8499 is a step down regulator that will handle a wide
input operating voltage range.
The A8499 is supplied in a low-profile 8-lead SOIC with
exposed pad (package LJ).
Applications include:
▪ Printer power supplies
▪ Consumer equipment power supplies
Package: 8-Lead SOIC with exposed
thermal pad (suffix LJ)
Approximate Scale 1:1
Typical Application
CBOOT
0.01 μF
BOOT
VIN
ENB
RTSET
121 kΩ
TSET
GND
A8499
LX
VBIAS
FB
D1
+42 V
C3
100 μF
50 V
C3
0.22 μF
L1
47 μH
R1
17.8 kΩ
R2
10.2 kΩ
VOUT
3.3 V / 1.2 A
ESR
COUT
220 μF
10 V
90.0
88.0
86.0
84.0
82.0
80.0
78.0
76.0
74.0
72.0
70.0
0
Efficiency vs. Output Current
VOUT (V)
3.3
5
200 400 600 800 1000 1200 1400
IOUT (mA)
Circuit for 42 V step down to 3.3 V at 1.2 A. Efficiency data from circuit shown in left panel.Data is for reference only.
A8499-DS, Rev. 3
1 page  
A8499
High Voltage Step-Down Regulator
The switching frequency is calculated as follows:
fSW =
1
tON + tOFF
(4)
Shorted Load. If the voltage on the FB pin falls below 0.5 V, the
regulator will invoke a 0.8 A typical overcurrent limit to handle
shorted load condition at the regulator output. For low output
voltages at power up and in the case of a shorted output, the off-
time is extended to prevent loss of control of the current limit due
to the minimum on-time of the switcher.
The extension of the off-time is based on the value of the TSET
multiplier and the FB voltage, as shown in the following table:
VFB (V)
< 0.25
< 0.50
< 0.75
> 0.75
TSET Multiplier
8 × tOFF
4 × tOFF
2 × tOFF
tOFF
Component Selection
L1. The inductor must be rated to handle the total load current.
The value should be chosen to keep the ripple current to a reason-
able value. The ripple current, IRIPPLE, can be calculated by:
IRIPPLE = VL(OFF) × tOFF / L
(5)
VL(OFF) = VOUT + Vf + IL(AVG) × RL
Example:
(6)
Given VOUT = 5 V, Vf = 0.55 V, VIN = 42 V, ILOAD = 0.5 A, power
inductor with L = 180 μH and RL = 0.5 Ω Rdc at 55°C, tOFF =
7 μs, and RDS(on) = 1 Ω.
Substituting into equation 6:
VL(OFF) = 5 V + 0.55 V+ 0.5 A × 0.5 Ω = 5.8 V
Substituting into equation 5:
IRIPPLE = 5.8 V × 7 μs / 180 μH = 225 mA
The switching frequency, fSW, can then be estimated by:
fSW = 1 / ( tON + tOFF )
(7)
tON = IRIPPLE × L / VL(ON)
(8)
VL(ON) = VIN – IL(AVG) × RDS(on) – IL(AVG) × RL– VOUT
Substituting into equation 9:
(9)
VL(ON) = 42 V – 0.5 A × 1 Ω – 0.5 A × 0.5 Ω – 5 V = 36 V
Substituting into equation 8:
tON = 225 mA × 180 μH / 36 V = 1.12 μs
Substituting into equation 7:
fSW = 1 / (7 μs +1.12 μs) = 123 kHz
Higher inductor values can be chosen to lower the ripple cur-
rent. This may be an option if it is required to increase the total
maximum current available above that drawn from the switching
regulator. The maximum total current available, ILOAD(MAX) , is:
ILOAD(MAX) = ICL(MIN) × tOFF / L
(5)
where ICL(MIN) is 2.2 A, from the Electrical Chracteristics table.
D1. The Schottky catch diode should be rated to handle 1.2 times
the maximum load current. The voltage rating should be higher
than the maximum input voltage expected during all operating
conditions. The duty cycle for high input voltages can be very
close to 100%.
COUT. The main consideration in selecting an output capacitor
is voltage ripple on the output. For electrolytic output capacitors,
a low-ESR type is recommended.
The peak-to-peak output voltage ripple is simply IRIPPLE × ESR.
Note that increasing the inductor value can decrease the ripple
current. The ESR should be in the range from 50 to 500 mΩ.
RTSET Selection. Correct selection of RTSET values will
ensure that minimum on time of the switcher is not violated and
prevent the switcher from cycle skipping. For a given VIN to
VOUT ratio, the RTSET value must be greater than or equal to
the value defined by the curve in the chart RTSET Value versus
VIN/VOUT , on the next page.
Note. The curve represents the minimum RTSET value. When
calculating RTSET , be sure to use VIN(max) / VOUT(min). Resistor
tolerance should also be considered, so that under no operating
conditions the resistance on the TSET pin is allowed to go below
the minimum value.
Allegro MicroSystems, Inc.
5
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet A8499.PDF ] | |
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