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PDF MTV112A Data sheet ( Hoja de datos )
| Número de pieza | MTV112A | |
| Descripción | 8051 Embedded CRT Monitor Controller MASK Version | |
| Fabricantes | Myson | |
| Logotipo |  |
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MYSON
TECHNOLOGY
MTV112A
(Rev 1.9)
8051 Embedded CRT Monitor Controller
MASK Version
FEATURES
l 8051 core.
l 384-bytes internal RAM.
l 16K-bytes program Mask ROM.
l 14-channels 10V open-drain PWM DAC, 10 dedicated channels and 4 channels shared with I/O pin.
l 28 bi-direction I/O pin,12 dedicated pin,12 shared with DAC,4 shared with DDC/IIC interface.
l 5-output pin shared with H/V sync output and self test output pins.
l SYNC processor for composite separation, polarity and frequency check, and polarity adjustment.
l Built-in monitor self-test pattern generator.
l Built-in low power reset circuit.
l One slave mode IIC interface and one master mode IIC interface.
l IIC interface for DDC1/DDC2B and EEPROM; only one EEPROM needed to store DDC1/DDC2B and
display mode information.
l Dual 4-bit ADC or 4 channel 6-bit ADC.
l Watchdog timer with programmable interval.
l 40-pin PDIP and 44-pin PLCC package.
GENERAL DESCRIPTION
The MTV112A micro-controller is an 8051 CPU core embedded device specially tailored to CRT monitor
applications. It includes an 8051 CPU core, 384-byte SRAM, 14 built-in PWM DACs, DDC1/DDC2B interface,
24Cxx series EEPROM interface, A/D converter and a 16K-bytes internal program Mask ROM.
BLOCK DIAGRAM
P1.0-7
P0.0-7
RD
X1 WR
8051
X2 CORE INT
1
P2.0-3
RST
P3.0-P3.2 P3.4 P2.4-7
P0.0-7
RD
WR
XFR
WATCH-DOG
TIMER
RST
HSCL
HSDA
DDC 1/2 B & FIFO
INTERFACE
STOUT
HSYNC
H / VSYNC VSYNC
CONTROL HBLANK
VBLANK
14 CHANNEL DA0-9
PWM DAC
DA10-13
ADC
AD0
AD1
ISCL
IIC INTERFACE
ISDA
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
1/20
MTV112A Revision 1.9 05/18/2001
1 page  
MYSON
TECHNOLOGY
MTV112A
(Rev 1.9)
P51E = 1 → Pin #38 is P5.1.
= 0 → Pin #38 is DA1.
P50E = 1 → Pin #39 is P5.0.
= 0 → Pin #39 is DA0.
MORE = 1 → Bits P57E,P56E,P55E,P54E,P53E,P52E,P51E,P50E,DACK,EHALFV,
EHALFH,ENCLP,ADCMOD can be programmed,and master IIC speed is
controlled by (MCLK1,MCLK0) bits.
= 0 → above bits internal keep “0” by MTV112A, and master IIC speed is controlled by
IICF bit.
* SINT0 should be 0 in this case.
2. Memory Allocation
2.1 Internal Special Function Registers (SFR)
SFR is a group of registers that is the same as standard 8051.
2.2 Internal RAM
There is a 384 bytes RAM in MTV112A. The first portion of the RAM area contains 256 bytes, accessible by
setting PSW.1=0; the second portion of the RAM area contains 128 bytes, accessible by setting PSW.1=1.
2.3 External Special Function Registers (XFR)
XFR is a group of registers allocated in the 8051 external RAM area. Most of the registers are used for
monitor control or PWM DAC. The program can initialize Ri value and use "MOVX" instruction to access
these registers.
FFH
80H
7FH
Accessible by indirect
addressing only.
The value of PSW.1 =
both 0 and 1.
(Using MOV A, @Ri
instruction)
Accessible by direct
and indirect
addressing.
PSW.1=0
00H
SFR
Accessible by direct
addressing.
Accessible by direct
and indirect
addressing.
PSW.1 =1
FFH
XFR
Accessible by indirect
external RAM
addressing.
(Using MOVX A, @Ri
00H Instruction.)
3. PWM DAC
Each D/A converter's output pulse width is controlled by an 8-bit register in XFR. The frequency of PWM clk
is X’tal or 2 * X’tal, selected by DACK. And the frequency of these DAC outputs is (PWM clk frequency)/253
or (PWM clk frequency)/256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to the DAC register
generates stable high output. If DIV253=0, the output will pulse low at least once even if the DAC register's
content is FFH. Writing 00H to the DAC register generates stable low output.
reg name
DA0
DA1
DA2
DA3
addr
20h (r/w)
21h (r/w)
22h (r/w)
23h (r/w)
bit7
DA0b7
DA1b7
DA2b7
DA3b7
bit6
DA0b6
DA1b6
DA2b6
DA3b6
bit5
DA0b5
DA1b5
DA2b5
DA3b5
bit4
DA0b4
DA1b4
DA2b4
DA3b4
bit3
DA0b3
DA1b3
DA2b3
DA3b3
bit2 bit1 bit0
DA0b2 DA0b1 DA0b0
DA1b2 DA1b1 DA1b0
DA2b2 DA2b1 DA2b0
DA3b2 DA3b1 DA3b0
MTV112A Revision 1.9 05/18/2001
5/20
5 Page 
MYSON
TECHNOLOGY
MTV112A
(Rev 1.9)
VCNTH (r) : V-Freq counter's high bits.
Vovf = 1 → V-Freq counter overflows; this bit is cleared by H/W when condition removed.
VF8 : High bit of V-Freq counter.
VCNTL (r) : V-Freq counter's low bits.
PCTR0 (w) : SYNC processor control register 0.
C1, C0 = 1,1 → Selects CVSYNC as the polarity, Freq and VBLANK source.
= 1,0 → Selects VSYNC as the polarity, Freq and VBLANK source.
= 0,0 → Disables composite function (MTV012 compatible mode).
= 0,1 → H/W auto switches to CVSYNC when CVpre=1 and VSpre=0.
HVsel = 1 → Pin #16 is P4.1, pin #17 is P4.0.
= 0 → Pin #16 is HBLANK, pin #17 is VBLANK.
STOsel = 1 → Pin #29 is P4.2.
= 0 → Pin #29 is STOUT.
PREFS = 0 → Selects 8MHz OSC as H/V presence check and self-test pattern time base.
= 1 → Selects 12MHz OSC as H/V presence check and self-test pattern time base.
HALFV = 1 → VBLANK is half frequency output of VSYNC.
HBpl = 1 → Negative polarity HBLANK output.
= 0 → Positive polarity HBLANK output.
VBpl = 1 → Negative polarity VBLANK output.
= 0 → Positive polarity VBLANK output.
PCTR2 (w) : Self-test pattern generator control.
Selft = 1 → Enables generator.
= 0 → Disables generator.
STbsh = 1 → 63.5KHz (horizontal) output selected.
= 0 → 31.75KHz (horizontal) output selected.
Rt1, Rt0= 0,0 → Positive cross-hatch pattern output.
= 0,1 → Negative cross-hatch pattern output.
= 1,0 → Full white pattern output.
= 1,1 → Full black pattern output.
STF = 1 → Enables STOUT output.
= 0 → Disables STOUT output.
PCTR3 (w) : HSYNC clamp pulse control register.
ENCLP = 1 → pin #4 is HCLAMP.
= 0 → pin #4 is P1.3.
CLPEG = 1 → Clamp pulse follows HSYNC leading edge.
= 0 → Clamp pulse follows HSYNC trailing edge.
CLPPO= 1 → Positive polarity clamp pulse output.
= 0 → Negative polarity clamp pulse output.
CLPW2 : CLPW0 : Pulse width of clamp pulse is
[(CLPW2:CLPW0) + 1] X 0.25 µs for 8MHz X’tal selection,or
[(CLPW2:CLPW0) + 1] X 0.167 µs for 12MHz X’tal selection.
EHALFV= 1 → pin #2 is HALFV.
= 0 → pin #2 is P1.1.
EHALFV= 1 → pin #3 is HALFH.
= 0 → pin #3 is P1.2.
P4OUT (w) : Port 4 data output value.
P5OUT (r/w) : Port 5 data input/output value.
11/20
MTV112A Revision 1.9 05/18/2001
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MTV112A.PDF ] | |
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