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PDF W77E516 Data sheet ( Hoja de datos )
| Número de pieza | W77E516 | |
| Descripción | 8-BIT MICROCONTROLLER | |
| Fabricantes | Winbond | |
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Preliminary W77E516
8-BIT MICROCONTROLLER
Table of Contents-
1. GENERAL DESCRIPTION...........................................................................................................................3
2. FEATURES ..................................................................................................................................................3
3. PIN CONFIGURATIONS..............................................................................................................................4
4. PIN DESCRIPTION......................................................................................................................................5
5. BLOCK DIAGRAM .......................................................................................................................................6
6. FUNCTIONAL DESCRIPTION.....................................................................................................................7
I/O Ports.....................................................................................................................................................7
Serial I/O....................................................................................................................................................7
Timers ........................................................................................................................................................8
Interrupts....................................................................................................................................................8
Data Pointers .............................................................................................................................................8
Power Management...................................................................................................................................8
On-chip Data SRAM ..................................................................................................................................8
7. MEMORY ORGANIZATION .........................................................................................................................8
Program Memory .......................................................................................................................................8
Data Memory .............................................................................................................................................9
Special Function Registers ......................................................................................................................10
Special Function Registers ......................................................................................................................11
Instruction ................................................................................................................................................34
Instruction Timing ....................................................................................................................................41
Power Management.................................................................................................................................49
Reset Conditions .....................................................................................................................................51
Reset State ..............................................................................................................................................52
Interrupts..................................................................................................................................................53
8. PROGRAMMABLE TIMERS/COUNTERS .................................................................................................56
Timer/Counters 0 & 1...............................................................................................................................56
Time-base Selection ................................................................................................................................57
Timer/Counter 2 .......................................................................................................................................59
Watchdog Timer ......................................................................................................................................62
Serial Port ................................................................................................................................................64
Framing Error Detection ..........................................................................................................................70
Multiprocessor Communications..............................................................................................................70
Publication Release Date: August 16, 2002
- 1 - Revision A1
1 page  
Preliminary W77E516
4. PIN DESCRIPTION
SYMBOL
EA
TYPE
DESCRIPTIONS
I
EXTERNAL ACCESS ENABLE: It should be kept high for internal program
access..
PSEN
ALE
RST
XTAL1
XTAL2
VSS
VDD
P0.0 − P0.7
P1.0 − P1.7
O PROGRAM STORE ENABLE: PSEN enables the external ROM data onto
the Port 0 address/data bus during fetch and MOVC operations.
O
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0.
I
RESET: A high on this pin for two machine cycles while the oscillator is running
resets the device.
I
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an
external clock.
O CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
I GROUND: Ground potential
I POWER SUPPLY: Supply voltage for operation.
I/O
PORT 0: Port 0 is an open-drain bi-directional I/O port. This port also provides
a multiplexed low order address/data bus during accesses to external memory.
PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have
alternate functions which are described below:
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture/Direction control
RXD1(P1.2): Serial port 1 RXD
I/O TXD1(P1.3): Serial port 1 TXD
INT2(P1.4): External Interrupt 2
INT3 (P1.5): External Interrupt 3
INT4(P1.6): External Interrupt 4
INT5 (P1.7): External Interrupt 5
P2.0 − P2.7
I/O
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory.
PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have
alternate functions, which are described below:
RXD(P3.0): Serial Port 0 input
TXD(P3.1): Serial Port 0 output
P3.0 − P3.7
INT0 (P3.2): External Interrupt 0
I/O INT1(P3.3): External Interrupt 1
T0(P3.4): Timer 0 External Input
T1(P3.5): Timer 1 External Input
WR (P3.6): External Data Memory Write Strobe
P4.0 − P4.3
RD (P3.7): External Data Memory Read Strobe
PORT 4: Port 4 is a 4-bit bi-directional I/O port. The P4.0 also provides the
I/O
alternate function WAIT which is the wait state control signal.
* Note: TYPE I: input, O: output, I/O: bi-directional.
Publication Release Date: August 16, 2002
- 5 - Revision A1
5 Page 
Preliminary W77E516
Special Function Registers
The W77E516 uses Special Function Registers (SFRs) to control and monitor peripherals and their
Modes.
The SFRs reside in the register locations 80-FFh and are accessed by direct addressing only. Some of
the SFRs are bit addressable. This is very useful in cases where one wishes to modify a particular bit
without changing the others. The SFRs that are bit addressable are those whose addresses end in 0 or
8. The W77E516 contains all the SFRs present in the standard 8052. However, some additional SFRs
have been added. In some cases unused bits in the original 8052 have been given new functions. The
list of SFRs is as follows. The table is condensed with eight locations per row. Empty locations indicate
that there are no registers at these addresses. When a bit or register is not implemented, it will read
high.
Table 1. Special Function Register Location Table
F8 EIP
F0 B
E8 EIE
E0 ACC
D8 WDCON
D0 PSW
C8 T2CON
C0 SCON1
B8 IP
T2MOD
SBUF1
SADEN
RCAP2L RCAP2H TL2
WSCON
PMR
SADEN1
B0 P3
A8 IE
A0 P2
SADDR
SADDR1
P4CSIN
SFRAL
98 SCON0
90 P1
88 TCON
SBUF
EXIF
TMOD
P42AL P42AH P43AL
P4CONA P4CONB P40AL
TL0 TL1 TH0
80 P0 SP DPL DPH DPL1
Note: The SFRs in the column with dark borders are bit-addressable.
TH2 NVMCON NVMDAT
STATUS NVMSEL TA
SFRAH
P4
P43AH
P40AH
TH1
DPH1
SFDFD SFRCN
P41AL
CKCON
DPS
CHPCON
P41AH
PCON
- 11 -
Publication Release Date: August 16, 2002
Revision A1
11 Page | ||
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| PDF Descargar | [ Datasheet W77E516.PDF ] | |
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