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PDF EN29LV640U Data sheet ( Hoja de datos )
| Número de pieza | EN29LV640U | |
| Descripción | (EN29LV640U / EN29LV641x) Flash Memory | |
| Fabricantes | EON | |
| Logotipo |  |
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EN29LV641H/L EN29LV640U
EN29LV641H/L EN29LV640U
64 Megabit (4096K x 16-bit) Flash Memory, CMOS 3.0 Volt-only
Uniform Sector Flash Memory
FEATURES
• Single power supply operation
- Full voltage range: 2.7 to 3.6 volts for read,
erase and program operations
• Low power consumption (typical values at 5
MHz)
- 9 mA typical active read current
- 20 mA typical program/erase current
- Less than 1 µA current in standby or automatic
sleep mode.
• JEDEC standards compatible
- Pinout and software compatible with single-
power supply Flash standard
• Manufactured on 0.18 m process
technology
• Flexible Sector Architecture:
- One hundred and twenty-eight 32K-Word
sectors.
• Minimum 100K program/erase endurance
cycles.
• High performance for program and erase
- Word program time: 8µs typical
- Sector Erase time: 500ms typical
- Chip Erase time: 64s typical
• Package Options
- 48-pin TSOP
- 63 ball 11mm x 12mm FBGA
Software features:
• Sector Group Protection
- Provide locking of sectors to prevent program
or erase operations within individual sectors
- Additionally, temporary Sector Group
Unprotect allows code changes in previously
protected sectors.
• Standard DATA# polling and toggle bits
feature
• Unlock Bypass Program command supported
• Sector Erase Suspend / Resume modes:
Read and program another Sector during
Sector Erase Suspend Mode
• Support JEDEC Common Flash Interface
(CFI).
Hardware features:
• RESET# hardware reset pin
- Hardware method to reset the device to read
mode.
• WP# input pin
- Write Protect (WP#) function allows
protection of first or last 32K-word sector,
regardless of previous sector protect status
• ACC input pin
- Acceleration (ACC) function provides
accelerated program times for higher
throughput for manufacturing.
GENERAL DESCRIPTION
The EN29LV641H/L / EN29LV640U is a 64-Megabit (4,194,304x16), electrically erasable, read/write
non-volatile flash memory. Any word can be programmed typically in 8µs. This device is entirely
command set compatible with the JEDEC single-power-supply Flash standard.
The EN29LV641H/L / EN29LV640U is designed to allow either single Sector or full Chip erase
operation, where each Sector Group can be protected against program/erase operations or
temporarily unprotected to erase or program. The device can sustain a minimum of 100K
program/erase cycles on each Sector.
This Data Sheet may be revised by subsequent versions 1
or modifications due to changes in technical specifications.
©2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
1 page  
ORDERING INFORMATION
EN29LV641 H
90 T
I
EN29LV641H/L EN29LV640U
P
PACKAGING CONTENT
(Blank) = Conventional
P = Pb Free
TEMPERATURE RANGE
I = Industrial (-40°C to +85°C)
C = Commercial (0°C to +70°C)
PACKAGE
T = 48-pin TSOP
W= 63-Ball Fine Pitch Ball Grid Array (FBGA)
0.80mm pitch, 11mm x 12mm package
SPEED OPTION
See Product Selector Guide and Valid Combinations
SECTOR for WRITE PROTECT (WP#=0)
H = highest address sector protected
L = lowest address sector protected
BASE PART NUMBER
EN29LV641 / EN29LV640U
64 Megabit(4M x 16-Bit) Uniform Sector Flash
Optional Data I/O voltage
3V Read, Erase and Program
PRODUCT SELECTOR GUIDE
Valid Combinations for TSOP Packages
EN29LV641H 90
EN29LV641L 90
EN29LV641H 70R,
EN29LV641L 70R
TI, TC
Vcc
Vcc = 2.7V-3.6V
Vcc = 3.0V-3.6V
Valid Combinations for FBGA Packages
EN29LV640U 90
EN29LV640U 70R
WI, WC
Vcc
Vcc = 2.7V-3.6V
Vcc = 3.0V-3.6V
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
5 Page 
EN29LV641H/L EN29LV640U
data with the same exception. See “Sector Erase Suspend/Resume Commands” for more additional
information.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes
high or while in the autoselect mode. See the “Reset Command” for additional details.
Output Disable Mode
When the OE# pin is at a logic high level (VBIHB), the output from the device is disabled. The output pins
are placed in a high impedance state.
Standby Mode
The device has a CMOS-compatible standby mode, which reduces the current to < 1µA (typical). It is
B
placed in CMOS-compatible standby when the CE# pin is at VCCB B ± 0.5. RESET# and BYTE# pin must
also be at CMOS input levels. The device also has a TTL-compatible standby mode, which reduces the
maximum
VBCC
current
B
to
<
1mA.
It is placed in TTL-compatible standby when the CE# pin is at V .IHB B
When in standby modes, the outputs are in a high-impedance state independent of the OE# input.
Automatic Sleep Mode
The device has an automatic sleep mode, which minimizes power consumption. The devices will enter
this mode automatically when the states of address bus remain stable for tacc + 30ns. ICC4 in the DC
Characteristics table shows the current specification. With standard access times, the device will output
new data when addresses change.
Writing Command Sequences
To write a command or command sequence to program data to the device or erase data, the system
has to drive WE# and CE# to VBIL, and OE# to V .IHB B
The device has an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to program a word, instead of four.
The system can also read the autoselect codes by entering the autoselect mode, which need the
autoselect command sequence to be written. Please refer to the “Command Definitions” for all the
available commands.
Autoselect Identification Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming
equipment to automatically match a device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be accessed in-system through the command
register.
When using programming equipment, the autoselect mode requires VIDB B (10.5 V to 11.5 V) on address
pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when
verifying sector group protection, the sector group address must appear on the appropriate highest
order address bits. Refer to the corresponding Sector Address Tables. The “Command Definitions”
table shows the remaining address bits that are don’t-care. When all necessary bits have been set as
required, the programming equipment may then read the corresponding identifier code on DQ15–DQ0.
To access the autoselect codes in-system; the host system can issue the autoselect command via the
command register, as shown in the Command Definitions table. This method does not require V .IDB B See
“Command Definitions” for details on using the autoselect mode. Note that a Reset command is
required to return to read mode when the device is in the autoselect mode.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
11 ©2005 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2005/06/27
11 Page | ||
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