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PDF ATF1502BE Data sheet ( Hoja de datos )
| Número de pieza | ATF1502BE | |
| Descripción | High Speed CPLD | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• High-performance Fully CMOS, Electrically-erasable Complex Programmable
Logic Device
– 32 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44 Pins
– 5.0 ns Pin-to-pin Propagation Delay
– Registered Operation up to 333 MHz
– Enhanced Routing Resources
– Optimized for 1.8V Operation
– 2 I/O Banks to Facilitate Multi-voltage I/O Operation: 1.8V, 2.5V, 3.3V
• In-System Programming (ISP) Supported
– 1.8V ISP Using IEEE 1532 (JTAG) Interface
– Boundary-scan Testing to IEEE JTAG Std. 1149.1 Supported
• Flexible Logic Macrocell
– D/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate with Low Output Drive
– Programmable Open Collector Output Option
– Maximum Logic Utilization by Burying a Register with a COM Output and Vice
Versa
• Fully Green (RoHS Compliant)
• 10 µA Static Current
• Power Saving Option During Operation Using PD1, PD2 Pins
• Programmable Pin-keeper Option on Inputs and I/Os
• Programmable Schmitt Trigger Option on Input and I/O Pins
• Programmable Input and I/O Pull-up Option (per Pin)
• Unused Pins Can Be Configured as Ground (Optional)
• Available in Commercial and Industrial Temperature Ranges
• Available in 44-lead TQFP
• Advanced Digital CMOS Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 10-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
• Security Fuse Feature
• Hot-Socketing Supported
High-
performance
CPLD
ATF1502BE
Rev. 3492A–PLD–12/05
1 page  
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ATF1502BE
1.3 Flip-flop
The ATF1502BE’s flip-flop has very flexible data and control functions. The data input can come
from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the
separate product term allows creation of a buried registered feedback within a combinatorial out-
put macrocell. (This feature is automatically implemented by the fitter software). In addition to D,
T, JK and SR operation, the flip-flop can also be configured as a flow-through latch. In this
mode, data passes through when the clock is high and is latched when the clock is low.
The clock itself can be any one of the Global CLK signals (GCK[0 : 2]) or an individual product
term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the
clock, one of the macrocell product terms can be selected as a clock enable. When the clock
enable function is active and the enable signal (product term) is low, all clock edges are ignored.
The flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a prod-
uct term, or always off. AR can also be a logic OR of GCLEAR with a product term. The
asynchronous preset (AP) can be a product term or always off.
1.4 Extra Feedback
The ATF1502BE macrocell output can be selected as registered or combinatorial. The extra bur-
ied feedback signal can be either combinatorial or a registered signal regardless of whether the
output is combinatorial or registered. (This enhancement function is automatically implemented
by the fitter software.) Feedback of a buried combinatorial output allows the creation of a second
latch within a macrocell.
1.5 I/O Control
The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be individ-
ually configured as an input, output or bi-directional pin. The output enable for each macrocell
can be selected from the true or complement of the two output enable pins, a subset of the I/O
pins, or a subset of the I/O macrocells. This selection is automatically done by the fitter software
when the I/O is configured as an input or bi-directional pin.
1.6 Global Bus/Switch Matrix
The global bus contains all input and I/O pin signals as well as the buried feedback signal from
all 32 macrocells. The switch matrix in each logic block receives as its inputs all signals from the
global bus. Under software control, up to 40 of these signals can be selected as inputs to the
logic block.
1.7 Foldback Bus
Each macrocell also generates a foldback product term. This signal goes to the regional bus and
is available to all 16 macrocells within the logic block. The foldback is an inverse polarity of one
of the macrocell’s product terms. The 16 foldback terms in each logic block allow generation of
high fan-in sum terms or other complex logic functions with little additional delay.
3492A–PLD–12/05
5
5 Page 
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ATF1502BE
Figure 6-1. BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins)
Note: The ATF1502BE has a pull-up option on TMS and TDI pins. This feature is selected as a design
option.
Figure 6-2. BSC Configuration for Macrocell
TDO
QD
0
1
CLOCK
TDI
OEJ
0
1
TDO
DQ
0
1
DQ
OUTJ
0 DQ
1
Capture
DR
DQ
Update
DR
TDI
Shift
Clock
BSC for I/O Pins and Macrocells
0
1
Mode
Pin
7. Design Software Support
ATF1502BE designs are supported by several third-party tools. Automated fitters allow logic
synthesis using a variety of high-level description languages such as VHDL® and Verilog®. Third
party synthesis and simulation tools from Mentor Graphics® are integrated into Atmel’s software
tools.
3492A–PLD–12/05
11
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| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ATF1502BE.PDF ] | |
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