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PDF W83194BR-648 Data sheet ( Hoja de datos )
| Número de pieza | W83194BR-648 | |
| Descripción | CLOCK GENERATOR | |
| Fabricantes | Winbond | |
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W83194BR-648
Data Sheet
WIBOND
CLOCK GENERATOR
FOR
SIS P4 SERIES CHIPSET
Publication Release Date: April 13, 2005
- I - Revision 1.1
1 page  
W83194BR-648
1. GENERAL DESCRIPTION
The W83194BR-648 is a Clock Synthesizer for SIS P4 series chipset. W83194BR-648 provides all
clocks required for high-speed Intel Pentium 4, and also provides 32 different frequencies of CPU
clocks frequency setting. All clocks are externally selectable with smooth transitions. The W83194BR-
648 makes SDRAM in synchronous or asynchronous frequency with CPU clocks.
The W83194BR-648 provides step-less frequency programming by controlling the VCO freq. and the
programmable AGP, PCI clock output divisor ratio. AGP and PCI frequency can be fixed to be four
kinds of different frequency outputs. A watchdog timer is quipped and when time out, register9 bit5 will
be set to 1 for warning. Spread spectrum built in at ±0.5% or ±0.25% to reduce EMI. Programmable
stopping individual clock outputs and frequency selection through I2C interface.
The W83194BR-648 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI CLOCK outputs typically provide greater than 1V /nS slew rate into 30 pF loads. The
fixed frequency outputs as REF, 24 MHz, and 48 MHz provide better than 0.5V /nS slew rate.
2. FEATURES
• Supports Intel Pentium 4 CPU with I2C.
• 2 pairs of differential CPU clocks
• 2 ZCLK for SIS chipsets
• 2 AGP clocks
• 1 SDRAM output clock for chipset
• 8 PCI synchronous clocks
• 1 24/48 MHz, 1 48 MHz
• 3 REF clocks
• Skew --- CPU to SDRAM < 1 ns, PCI to PCI < 500ps, AGP to AGP < 175ps
• Smooth frequency switch with selections from 66 to 200 MHz
• I2C 2-Wire serial interface and I2C read back
• Flexible spread spectrum to reduce EMI
• Programmable registers to enable/stop each output
• Packaged in 48-pin SSOP
Publication Release Date: April 13, 2005
- 1 - Revision 1.1
5 Page 
W83194BR-648
7. I2C CONTROL AND STATUS REGISTERS
The Register 0~3 are reserved for external clock buffer
(The register No. Is increased by 1 if use byte data read/write protocol)
7.1 Register 4: Frequency Select (Default = 00H)
BIT
NAME
PWD
DESCRIPTION
7 SSEL [3] 0
6 SSEL [2] 0 Frequency selection by software via I2C
5 SSEL [1] 0
4 SSEL [0] 0
Enable software program FS [4:0].
3 EN_SSEL 0 0 = Select frequency by hardware.
1 = Select frequency by software I2C - Bit 4:7, 2.
2 SSEL [4] 0 Frequency selection bit 4
Enable Spread Spectrum in the frequency table.
1 EN_SPSP 0 0 = Normal
1 = Spread Spectrum enabled
Enable reload safe frequency when the watchdog is timeout.
0 EN_SAFE_FREQ 0 0 = reload the FS [4:0] latched pins when watchdog time out.
1 = reload the safe frequency bit defined at Register 9 bit 4~0.
7.2 Register 5: CPU, SDRAM Clock (1 = Enable, 0 = Stopped) (Default = FFH)
BIT
PIN NO
PWD
DESCRIPTION
7 47 1 SDRAM output control
6 44, 43 1 CPUCLKT/C1 output control
5 40, 39 1 CPUCLKT/C0 output control
4 15 X Invert Power on latched value of FS4 pin, Default 1 (Read only)
3 14 X Invert Power on latched value of FS3 pin. Default 1 (Read only)
2 4 X Invert Power on latched value of FS2 pin. Default 1 (Read only)
1 3 X Invert Power on latched value of FS1 pin. Default 1 (Read only)
0 2 X Invert Power on latched value of FS0 pin. Default 1 (Read only)
Publication Release Date: April 13, 2005
- 7 - Revision 1.1
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet W83194BR-648.PDF ] | |
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