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PDF 54ACT112 Data sheet ( Hoja de datos )
| Número de pieza | 54ACT112 | |
| Descripción | Dual JK Negative Edge-Triggered Flip-Flop | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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September 1998
54ACT112
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The ’ACT112 contains two independent, high-speed JK
flip-flops with Direct Set and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trigger-
ing occurs at a voltage level of the clock and is not directly
related to the transition time. The J and K inputs can change
when the clock is in either state without affecting the flip-flop,
provided that they are in the desired state during the recom-
mended setup and hold times relative to the falling edge of
the clock. A LOW signal on SD or CD prevents clocking and
forces Q or Q HIGH, respectively. Simultaneous LOW sig-
nals on SD and CD force both Q and Q HIGH.
Asynchronous Inputs:
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q
HIGH
Features
n ’ACT112 has TTL-compatible inputs
n Outputs source/sink 24 mA
n Standard Microcircuit Drawing (SMD) 5962-8995001
Connection Diagram
Pin Assigment for
DIP and Flatpack
Pin Descriptions
Pin Names
J1, J2, K1, K2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q2, Q1, Q2
Description
Data Inputs
Clock Pulse Inputs
(Active Falling Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
DS100976-3
Pin Assigment
for LCC
DS100976-5
FACT™ is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100976
www.national.com
1 page  
AC Electrical Characteristics for ’ACT Family Devices
Symbol
Parameter
fmax Maximum Clock
Frequency
tPLH Propagation Delay
CPn to Qn or Qn
tPHL Propagation Delay
CPn to Qn or Qn
tPLH Propagation Delay
CDn or SDn to Qn or Qn
tPHL Propagation Delay
CDn or SDn to Qn or Qn
Note 4: Voltage Range 5.0 is 5.0V ±0.5V
VCC
(V)
(Note
4)
5.0
5.0
5.0
5.0
5.0
TA = −55˚C to +125˚C
CL = 50 pF
Min Max
80
1.0 14.0
1.0 14.0
1.0 13.5
1.0 13.5
Units
MHz
ns
ns
ns
ns
AC Operating Requirements:
Symbol
Parameter
tS Setup Time, HIGH or
LOW
Jn or Kn to CPn
tH Hold Time, HIGH or
LOW
Jn or Kn to CPn
tW Pulse Width
CPn or CDn or SDn
trec Recovery Time
CDn or SDn to CPn
Note 5: Voltage Range 5.0 is 5.0V ±0.5V
VCC
(V)
(Note 5)
5.0
5.0
5.0
5.0
TA = −55˚C to +125˚C
CL = 50 pF
Guaranteed Minimum
8.0
1.5
5.0
3.0
Units
ns
ns
ns
ns
Capacitance
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Max
10.0
60
Units
pF
pF
Conditions
VCC = OPEN
VCC = 5.0V
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 54ACT112.PDF ] | |
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