PDF ZL30110 Data sheet ( Hoja de datos )

Número de pieza	ZL30110
Descripción	Telecom Rate Conversion DPLL
Fabricantes	Zarlink Semiconductor
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No Preview Available ! www.DataSheet4U.com ZL30110 Telecom Rate Conversion DPLL Features • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz • Provides a range of output clocks: • 65.536 MHz TDM clock locked to the input reference • General purpose 25 MHz fan-out to 6 outputs locked to the external crystal or oscillator • General purpose 125 MHz and 66 MHz or 100 MHz locked to the external crystal or oscillator • Provides DPLL lock and reference fail indication • Automatic free run mode on reference fail • DPLL bandwidth of 922 Hz for all rates of input reference and 58 Hz for an 8 kHz input reference • Less than 5 psecrms on 25 MHz outputs, and less than 0.6 nspp intrinsic jitter on the all other outputs • Minimal input to output and output to output skew • 25 MHz external master clock source: clock oscillator or crystal • Simple hardware control interface Data Sheet November 2006 Ordering Information ZL30110LDE ZL30110LDE1 32 Pin QFN Tubes Bake & Dry Pack 32 Pin QFN* Tubes Bake & Dry Pack *Pb Free Matte Tin -40°C to +85°C Applications • Clock rate conversion PLL for Telecommunication Equipment • Small/Medium Enterprise Router / Gateway • Broadband access (xPON/xDSL) CPE gateway Description The ZL30110 clock rate conversion digital phase- locked loop (DPLL) provides accurate and reliable frequency conversion. The ZL30110 generates a range of clocks that are either locked to the input reference or locked to the external crystal or oscillator. In the locked mode, the reference input is continuously monitored for a failure condition. In the event of a failure, the DPLL continues to provide a stable free running clock ensuring system reliability. REF RST OSCi OSCo Reference Monitor State Machine Master Clock REF_FAIL LOCK DPLL Frequency Synthesizer Select MUX APLL APLL C65o OUT_SEL C100/66o C125o 6 X C25o Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved. 1 page ZL30110 Data Sheet List of Tables Table 1 - Clock Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 2 - Crystal Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Zarlink Semiconductor Inc. 5 Page ZL30110 Data Sheet 4.0 Measures of Performance The following are some PLL performance indicators and their corresponding definitions. 4.1 Jitter Timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. Wander is defined as the low-frequency variation of the clock edges from their ideal positions in time. High and low frequency variation imply phase oscillation frequencies relative to some demarcation frequency. (Often 10 Hz or 20 Hz for DS1 or E1, higher for SONET/SDH clocks.) Jitter parameters given in this data sheet are total timing jitter numbers, not cycle-to-cycle jitter. 4.2 Jitter Generation (Intrinsic Jitter) Jitter generation is the measure of the jitter produced by the PLL and is measured at its output. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Jitter is usually measured with various band limiting filters depending on the applicable standards. 4.3 Jitter Transfer Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. 4.4 Lock Time This is the time it takes the PLL to frequency lock to the input signal. Phase lock occurs when the input signal and output signal are aligned in phase with respect to each other within a certain phase distance (not including jitter). Lock time is affected by many factors which include: • initial input to output phase difference • initial input to output frequency difference • PLL loop filter bandwidth The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and frequency. 11 Zarlink Semiconductor Inc. 11 Page

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