PDF ZL30123 Data sheet ( Hoja de datos )

Número de pieza	ZL30123
Descripción	Low Jitter Line Card Synchronizer
Fabricantes	Zarlink Semiconductor
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No Preview Available ! www.DataSheet4U.com ZL30123 SONET/SDH Low Jitter Line Card Synchronizer Data Sheet A full Design Manual is available to qualified customers. To register, please send an email to [email protected]. Features • Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813 • Internal APLL provides standard output clock frequencies up to 622.08 MHz with jitter < 3 ps RMS suitable for GR-253-CORE OC-12 and G.813 STM-16 interfaces • Programmable output synthesizers (P0, P1) generate clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz • Provides two DPLLs which are independently configurable through a serial peripheral interface • DPLL1 provides all the features necessary for generating SONET/SDH compliant clocks including automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), and selectable loop bandwidth Ordering Information May 2006 ZL30123GGG 100 Pin CABGA Trays ZL30123GGG2 100 Pin CABGA* Trays Pb Free Tin/Silver/Copper -40oC to +85oC • DPLL2 provides a comprehensive set of features for generating derived output clocks and other general purpose clocks • Provides 8 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz • Provides 3 sync inputs for output frame pulse alignment • Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency • Configurable input to output delay, and output to output phase alignment • Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities • Supports IEEE 1149.1 JTAG Boundary Scan osco osci ref0 ref1 ref2 ref3 ref4 ref5 ref6 ref7 sync0 sync1 sync2 int_b trst_b tck tdi tms tdo dpll2_ref dpll1_hs_en dpll1_lock dpll1_holdover diff0_en diff1_en Master Clock IEEE 1449.1 JTAG ref7:0 sync2:0 Reference ref_&_sync_status Monitors DPLL2 ref ref DPLL1 sync fb_clk/fp P0 Synthesizer P1 Synthesizer SONET/SDH APLL Feedback Synthesizer p0_clk0 p0_clk1 p0_fp0 p0_fp1 p1_clk0 p1_clk1 diff0 diff1 sdh_clk0 sdh_clk1 sdh_fp0 sdh_fp1 fb_clk SPI Interface Controller & State Machine sck si so cs_b rst_b dpll1_mod_sel1:0 sdh_filter filter_ref0 filter_ref1 Figure 1 - Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved. 1 page ZL30123 Data Sheet List of Tables Table 1 - DPLL1 and DPLL2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4 - Output Clock and Frame Pulse Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5 - Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 Zarlink Semiconductor Inc. 5 Page ZL30123 Data Sheet 1.0 Functional Description The ZL30123 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. It incorporates two independent DPLLs, each capable of locking to one of eight input references and provides a wide variety of synchronized output clocks and frame pulses. 1.1 DPLL Features The ZL30123 provides two independently controlled Digital Phase-Locked Loops (DPLL1, DPLL2) for clock and/or frame pulse synchronization. Table 1 lists the feature summary for both DPLLs. Feature DPLL1 DPLL2 Modes of Operation Loop Bandwidth Free-run, Normal (locked), Holdover User selectable: 14 Hz, 28 Hz, or wideband1 (890 Hz / 56 Hz / 14 Hz) Free-run, Normal (locked), Holdover. Fixed: 14 Hz Phase Slope Limiting Pull-in Range User selectable: 885 ns/s, 7.5 µs/s, 61 µs/s, or unlimited Fixed: 130 ppm User selectable: 61 µs/s, or unlimited Fixed: 130 ppm Reference Inputs Ref0 to Ref7 Ref0 to Ref7 Sync Inputs Sync0, Sync1, Sync2 Sync inputs are not supported. Input Ref Frequencies 2 kHz, N 8 kHz up to 77.76 MHz 2 kHz, N * 8 kHz up to 77.76 MHz Supported Sync Input Frequencies 166.67 Hz, 400 Hz, 1 kHz, 2 kHz, 8 kHz, 64 kHz. Sync inputs are not supported. Input Reference Selection/Switching Automatic (based on programmable priority and revertiveness), or manual Automatic (based on programmable priority and revertiveness), or manual Hitless Ref Switching Can be enabled or disabled Can be enabled or disabled Output Clocks diff0_p/n, diff1_p/n, sdh_clk0, sdh_clk1, p0_clk0, p0_clk1, p1_clk0, p1_clk1, fb_clk. p0_clk0, p0_clk1, p1_clk0, p1_clk1. Output Frame Pulses sdh_fp0, sdh_fp1, p0_fp0, p0_fp1 p0_fp0, p0_fp1 not aligned to sync synchronized to active sync reference. reference. Supported Output Clock As listed in Table 4 Frequencies As listed in Table 4 for p0_clk0, p0_clk1, p1_clk0, p1_clk1 Supported Output Frame Pulse Frequencies As listed in Table 4 As listed in Table 4 for p0_fp0, p0_fp not aligned to sync reference. External Pins Status Indicators Lock, Holdover None Table 1 - DPLL1 and DPLL2 Features 1. In the wideband mode, the loop bandwidth depends on the frequency of the reference input. For reference frequencies equal to or greater than 64 kHz, the loop bandwidth = 890 Hz. For reference frequencies equal to or greater than 8 kHz and less than 64 kHz, the loop bandwidth = 56 Hz. For reference frequencies equal to 2 kHz, the loop bandwidth is equal to 14 Hz. 11 Zarlink Semiconductor Inc. 11 Page

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