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SY100ELT22 fiches techniques PDF

Micrel Semiconductor - DUAL TTL-to-DIFFERENTIAL PECL TRANSLATOR

Numéro de référence SY100ELT22
Description DUAL TTL-to-DIFFERENTIAL PECL TRANSLATOR
Fabricant Micrel Semiconductor 
Logo Micrel Semiconductor 





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SY100ELT22 fiche technique
Micrel, Inc.
www.DataSheet4U.com
DUAL TTL-to-DIFFERENTIAL
PECL TRANSLATOR
SY10ELT22
SY1S0YE1L00TE2L2T22
SY100ELT22
FEATURES
300ps typical propagation delay
<100ps output-to-output skew
Differential PECL outputs
PNP TTL inputs for minimal loading
Flow-through pinouts
Available in 8-pin SOIC package
DESCRIPTION
The SY10/100ELT22 are dual TTL-to-differential PECL
translators. Because PECL (Positive ECL) levels are
used, only +5V and ground are required. The small outline
8-lead SOIC package and the low skew, dual gate design
of the ELT22 makes it ideal for applications which require
the tranlation of a clock and a data signal.
The ELT22 is available in both ECL standards: the
10ELT is compatible with positive ECL 10H logic levels,
while the 100ELT is compatible with positive ECL 100K
logic levels.
PIN NAMES
Pin
Qn
Dn
VCC
GND
Function
Differential PECL Outputs
TTL Inputs
+5.0V Supply
Ground
M9999-120705
[email protected] or (408) 955-1690
1
Rev.: G Amendment: /0
Issue Date: December 2005

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