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Número de pieza | 74VCXH16374 | |
Descripción | Low-Voltage 1.8/2.5/3.3V 16-Bit D-Type Flip-Flop | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
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74VCXH16374
Low−Voltage 1.8/2.5/3.3V
16−Bit D−Type Flip−Flop
With 3.6 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
The 74VCXH16374 is an advanced performance, non−inverting
16−bit D−type flip−flop. It is designed for very high−speed, very
low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The VCXH16374
is byte controlled, with each byte functioning identically, but
independently. Each byte has separate Output Enable and Clock Pulse
inputs. These control pins can be tied together for full 16−bit operation.
When operating at 2.5 V (or 1.8 V) the part is designed to tolerate
voltages it may encounter on either inputs or outputs when interfacing
to 3.3 V busses. It is guaranteed to be overvoltage tolerant to 3.6V.
The 74VCXH16374 consists of 16 edge−triggered flip−flops with
individual D−type inputs and 3.6 V−tolerant 3−state outputs. The
clocks (CPn) and Output Enables (OEn) are common to all flip−flops
within the respective byte. The flip−flops will store the state of
individual D inputs that meet the setup and hold time requirements on
the LOW−to−HIGH Clock (CP) transition. With the OE LOW, the
contents of the flip−flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. The OE input level
does not affect the operation of the flip−flops. The data inputs include
active bushold circuitry, eliminating the need for external pullup
resistors to hold unused or floating inputs at a valid logic state.
Features
• Designed for Low Voltage Operation: VCC = 1.65 V − 3.6 V
• 3.6 V Tolerant Inputs and Outputs
• High Speed Operation: 3.0 ns max for 3.0 V to 3.6V
3.9 ns max for 2.3 V to 2.7V
7.8 ns max for 1.65 V to 1.95V
• Static Drive: ±24 mA Drive at 3.0 V
±18 mA Drive at 2.3 V
±6 mA Drive at 1.65 V
• Supports Live Insertion and Withdrawal
• Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
Logic State
• IOFF Specification Guarantees High Impedance When VCC = 0 V*
• Near Zero Static Supply Current in All Three Logic States (20 mA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds ±250 mA @ 125°C
• ESD Performance: Human Body Model >2000 V
Machine Model >200 V
• All Devices in Package TSSOP are Inherently Pb−Free**
*To ensure the outputs activate in the 3−state condition, the output enable pins
should be connected to VCC through a pullup resistor. The value of the resistor
is determined by the current sinking capability of the output connected to the
OE pin.
**For additional information on our Pb−Free strategy and soldering details,
please download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING DIAGRAM
48
48
1
TSSOP−48
DT SUFFIX
CASE 1201
VCXH16374
AWLYYWW
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PIN NAMES
Pins
Function
OEn
CPn
D0−D15
O0−O15
Output Enable Inputs
Clock Pulse Inputs
Inputs
Outputs
ORDERING INFORMATION
Device
Package
Shipping†
74VCXH16374DT
TSSOP
(Pb−Free)
39 / Rail
74VCXH16374DTR TSSOP
(Pb−Free)
2500 / Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 5
1
Publication Order Number:
74VCXH16374/D
1 page 74VCXH16374
AC CHARACTERISTICS (Note 6; tR = tF = 2.0 ns; CL = 30 pF; RL = 500 W)
TA = −40°C to +85°C
VCC = 3.0 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 1.65 V to 1.95 V
Symbol
Parameter
Waveform Min Max Min Max
Min
Max
Unit
fmax Clock Pulse Frequency
1 250
200
100
tPLH Propagation Delay
tPHL
CP−to−On
1
0.8 3.0 1.0 3.9
1.5
0.8 3.0 1.0 3.9
1.5
tPZH
tPZL
Output Enable Time to
High and Low Level
2
0.8 3.5 1.0 4.6
1.5
0.8 3.5 1.0 4.6
1.5
tPHZ Output Disable Time From 2 0.8 3.5 1.0 3.8 1.5
tPLZ High and Low Level
0.8 3.5 1.0 3.8
1.5
ts Setup Time, High or Low
Dn−to−CP
3 1.5
1.5
2.5
MHz
7.8 ns
7.8
9.2 ns
9.2
6.8 ns
6.8
ns
th Hold Time, High or Low
Dn−to−CP
3 1.0
1.0
1.0
ns
tw CP Pulse Width, High
3 1.5
1.5
4.0
ns
tOSHL
tOSLH
Output−to−Output Skew
(Note 7)
0.5 0.5
0.5 0.5
0.75 ns
0.75
6. For CL = 50 pF, add approximately 300 ps to the AC maximum specification.
7. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
AC CHARACTERISTICS (tR = tF = 2.0 ns; CL = 50 pF; RL = 500 W)
TA = −40°C to +85°C
VCC = 3.0 V to 3.6 V
Symbol
Parameter
Waveform
Min
Max
VCC = 2.7 V
Min Max
Unit
fmax Clock Pulse Frequency
4
150
150 MHz
tPLH Propagation Delay
tPHL
CP−to−On
4 1.0
1.0
4.2
4.2
4.9 ns
4.9
tPZH
tPZL
Output Enable Time to
High and Low Level
5
1.0
1.0
4.8
4.8
5.9 ns
5.9
tPHZ
tPLZ
Output Disable Time From
High and Low Level
5
1.0
1.0
4.3
4.3
4.7 ns
4.7
tOSHL
tOSLH
Output−to−Output Skew
(Note 8)
0.5 0.5 ns
0.5 0.5
8. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
http://onsemi.com
5
5 Page 74VCXH16374
PACKAGE DIMENSIONS
48
L
1
PIN 1
IDENT.
D
0.076 (0.003)
−T− SEATING
PLANE
C
TSSOP
DT SUFFIX
CASE 1201−01
ISSUE A
48X K REF
0.12 (0.005) M T U S
A
−V−
G
VS
25
24
J JÇÇÇÉÉÉ1 ÇÇÇÉÉÉKK1ÇÇÇÉÉÉ
SECTION N−N
B
−U−
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
FM
DETAIL E 0.25 (0.010)
DETAIL E
H
−W−
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 12.40 12.60 0.488 0.496
B 6.00 6.20 0.236 0.244
C −−− 1.10 −−− 0.043
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.50 BSC
0.0197 BSC
H 0.37 −−− 0.015 −−−
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.17 0.27 0.007 0.011
K1 0.17 0.23 0.007 0.009
L 7.95 8.25 0.313 0.325
M 0_ 8_ 0_ 8_
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
11
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
74VCXH16374/D
11 Page |
Páginas | Total 11 Páginas | |
PDF Descargar | [ Datasheet 74VCXH16374.PDF ] |
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