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PDF CD4541 Data sheet ( Hoja de datos )
| Número de pieza | CD4541 | |
| Descripción | PROGRAMMABLE TIMER CMOS IC | |
| Fabricantes | Unisonic Technologies | |
| Logotipo |  |
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UNISONIC TECHNOLOGIES CO., LTD
CD4541
PROGRAMMABLE TIMER
DESCRIPTION
The CD4541 programmable timer comprise a 16-stage
binary counter, an integrated oscillator for use with an external
capacitor and two resistors, output control logic, and a special
power-on reset circuit. The counter divides the oscillator
frequency by any of 4 digitally controlled division ratios.
FEATURES
* Operates at 2n frequency divider or as single transition timer
* Increments on positive edge clock transitions
* Wide supply voltage range: 3.0V ~ 15V
* Built-in low power RC oscillator
* Oscillator frequency range ~ DC to 100 kHz
* External clock applied to Pin 3 can be used instead of
* oscillator
* Available division ratios 28, 210, 213, or 216
* High noise immunity: 0.45 VDD (typ)
* Master reset totally independent of automatic reset operation
* Automatic reset initializes all counters when power turns on
* Q/Q select provides output logic level flexibility
* High output drive min. one TTL load
* Maximum input leakage 1μA at 15V over full temperature
* range
ORDERING INFORMATION
Ordering Number
Lead Free
Halogen Free
CD4541-D14-T
CD4541L-D14-T
- CD4541L-S14-R
- CD4541L-P14-T
Package
DIP-14
SOP-14
TSSOP-14
CMOS IC
Packing
Tube
Tape Reel
Tube
MARKING
DIP-14
SOP-14 / TSSOP-14
www.unisonic.com.tw
Copyright © 2015 Unisonic Technologies Co., Ltd
1 of 7
QW-R502-037.D
1 page  
CD4541
CMOS IC
OPERATING CHARACTERISTICS
With Auto Reset pin set to a “0” the counter circuit is initialized by turning on power. Or with power already on, the
counter circuit is reset when the Master Reset pin is set to a “1”. Both types of reset will result in synchronously
resetting all counter stages independent of counter state.
The RC oscillator frequency is determined by the external RC network, i.e.:
and RS ~ 2 RTC where RS≧10 kΩ
The time select inputs (A and B) provide a two-bit address to output any one of four counter stages (28, 210, 213,
and 216). The 2n counts as shown in the Division Ratio Table represent the Q output of the Nth stage of the counter.
When A is “1”, 216 is selected for both states of B.
However, when B is “0”, normal counting is interrupted and the 9th counter stage receives its clock directly from
the oscillator (i.e., effectively outputting 28).
The Q/Q select output control pin provides for a choice of output level. When the counter is in a reset condition
and Q/Q select pin is set to a “0” the Q output is a “0”. Correspondingly, when Q/Q select pin is set to a “1” the Q
output is a “1”.
When the mode control pin is set to a “1”, the selected count is continually transmitted to the output. But, with
mode pin “0” and after a reset condition the RS flip-flop resets (see Logic Diagram), counting commences and after
2n-1 counts the RS flip-flop sets which causes the output to change state. Hence, after another 2n-1 counts the output
will not change. Thus, a Master Reset pulse must be applied or a change in the mode pin level is required to reset
the single cycle operation.
Oscillator Circuit Using RC Configuration
3
INTERNAL
RESET
21
RS CTC RTC
TO CLOCK
CIRCUIT
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
5 of 7
QW-R502-037.D
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