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PDF U3500BM Data sheet ( Hoja de datos )
| Número de pieza | U3500BM | |
| Descripción | Cordless Telephone Signal Processor | |
| Fabricantes | TEMIC Semiconductors | |
| Logotipo |  |
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Cordless Telephone Signal Processor
U3500BM
Description
The programmable cordless phone signal processor
includes all necessary low frequency parts such as
microphone- and earphone amplifier, compander, pre-
emphasis, deemphasis, scrambler, data management,
power-supply management, as well as RF receiving parts
such as IF converter, FM demodulator. RSSI and low
noise amplifier.
Several gains and mutes in transmit and receive direction
are controlled by serial bus while compander, pre- and
deemphasis and scrambler can be bypassed.
Features
RF Receiver Part
D Low-noise amplifier
D IF converter
D FM demodulator
D RSSI
Low Frequency Part
D Symmetrical input of microphone amplifier
D Symmetrical output of earpiece amplifier
Block Diagram
MIXO IFIN1 IFIN2
D Compander
D Pre- and deemphasis
D Scrambler
D Data management
D Power-supply management
D Serial bus
Application: CT0
DACO
MIXIN
MIXGND
LOIN
LNAIN
RGND
LNAO
VBATT
C
D
IFAMP
LOG
www.DataSheet4U.com
Demodulator
RGAIN
ADJ
LPF
Oscillator
11.15 MHz
LNA
Divider
D/A
LPF
Serial
Bus
Battery low
detector
LPF
Scrambler
frequency
LPF
TGAIN
ADJ.2
Limiter
LPF Deem
Scrambler
frequency
Expander
REC
MIC
Preem
TGAIN
ADJ.1
Compressor
RXO
ETC
EXIN
RECO2
RECO1
MIC1
MIC2
MICO
RXDAT
TXDAT
COIN
VCC TXO
Figure 1. Block diagram
GND
CTC 14678
Rev. A3, 20-May-98
Preliminary Information
1 (17)
1 page  
U3500BM
Parameters
RF demodulator
BSCR EDEE
10
Recovered audio
Test Conditions / Pins
Symbol Min. Typ.
fIF = 450 kHz, fMOD = 1 kHz, VIF = 500 m Vrms
GRX0
GRX1
GRX2
GRX3
ERX1
11101
GDEM = 0, D fFM = 2.5 kHz
GDEM = 1, D fFM = 5.0 kHz
0.4 0.8
0.4 0.8
Recovered audio output
voltage drop
VBatt = 3.1 to 5.2 V
–1
AM rejection ratio
30% AM
30 35
RX audio
Change of RX0 signal
deemphasis bypass
EDEE = 0
–0.5 0
Gain adjust range
12 15
Gain adjust step
0.8 1
Output signal vs. frequency
relative to 1 kHz (0 dB)
deemphasis bypassed
100 Hz
300 Hz
1800 Hz
3200 Hz
4100 Hz
–7.5 –6.5
–2.0 –1.0
–1.3 –0.3
–0.8 0.2
Output signal vs. frequency
relative to 1 kHz (0 dB)
deemphasis enable
EDEE = 1
100 Hz
300 Hz
1800 Hz
3200 Hz
4100 Hz
–0.7 0.3
3.7 4.7
–5.7 –4.7
–10 –9.0
Total harmonic distortion
Audio mute
D FM = 250 Hz
D FM = 2.50 kHz
D FM = 2.5 kHz, ERXO = 0
ERX1 = 0, ERX2 = 0
65
Output impedance
Expander
EEA
GEA0
GEA1
GEA2
GEA3
10001
Gain reference level
Change of gain when
expander is bypassed
VEXIN = –10 dBVrms
BCOMP = 1
GOREC 11
–0.5
13
Gain tracking
Input impedance
VEXIN = –20 dBVrms
VEXIN = –30 dBVrms
VEXIN = –35 dBVrms
VEXIN = –40 dBVrms
–21
–41
–53 –50
–60
9.5
Gain change vs. supply
voltage
VBatt = 3.1 to 5.2 V
–0.5
Attack time
³VEXIN = step
–20 dBVrms –14 dBVrms,
measure time after step, when
output voltage has 0.75 times
the final value
tf
16
Release time
VEXIN = step
³14 dBVrms –20 dBVrms,
measure time after step, when
output voltage has 1.5 times of
the final value
tf
16
Max. Unit Fig.
ERXO
1
1.6
1.6
+1
ERX2
1
Vpp
Vpp
6
dB 6
dB 6
0.5 dB
17 dB
1.2 dB
–5.5
0
0.7 dB
1.2
–60
1.3
5.7
–3.7 dB
–8.0
–66
3.5 %
3.5 %
dB
100
GEA4
1
15
0.5
W
dB
dB
–19
–39 dB
–47
14.5 kW
0.5 dB
ms
6
6
6
6
6
6
6
7
7
7
7
7
7
ms
7
Rev. A3, 20-May-98
Preliminary Information
5 (17)
5 Page 
U3500BM
Gain stage
F–3 dB=3.35 kHz
DATA
F–3 dB=3.95 kHz
Output buffer
Demo–
dulator
F–3 dB=90 Hz
RGAIN
ADJ
Signal: 4.1 kHz/DC/OFF
State : SCRON/SCROFF/DATA
Gain : –4 dB/0 dB/OFF
F–3 dB=3.95 kHz
Signal: 1 kHz
State : SCRON/SCROFF
Gain : 5.9 dB/1.9 dB
F–3 dB=3.35 kHz
Deemphasis
DATA
Signal: 4.1 kHz/DC/OFF
State : DESCRON/DESCROFF/DATA
Gain : –4 dB/0 dB/OFF
F–3 dB=1 kHz
Comparator
Figure 11.
Signal: 1 kHz
State : DESCRON/DESCROFF
Gain : –0.5 dB/–4.5 dB
11786
Serial Bus Interface
The circuit is remoted by an external microcontroller
through the serial bus (programming can be started 10 m s
after power supply settled).
The data is an 12-bit word:
A3 – A0: address of the destination register (0 to 15)
D7 – D0: contents of register
The data line must be stable when the clock is high and
data must be serially shifted.
After 12 clock periods, the transfer to the destination reg-
ister is (internally) generated by a low-to-high transition
of the data line when the clock is high.
Micro-
processor
Data
Clock
Figure 12.
D
C
96 11787
Rev. A3, 20-May-98
Preliminary Information
11 (17)
11 Page | ||
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| PDF Descargar | [ Datasheet U3500BM.PDF ] | |
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