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Allegro MicroSystems - (ATS673 / ATS674) Self-Calibrating TPOS Gear Tooth Sensor Optimized

Numéro de référence ATS674
Description (ATS673 / ATS674) Self-Calibrating TPOS Gear Tooth Sensor Optimized
Fabricant Allegro MicroSystems 
Logo Allegro MicroSystems 





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ATS674 fiche technique
ATS673 and ATS674
Self-Calibrating TPOS Gear Tooth Sensor Optimized for
Automotive Cam Sensing Applications
Features and Benefits
Tight timing accuracy over operating temperature range
True zero-speed operation
TPOS (True Power-On State)
Air-gap-independent switchpoints
High immunity to vibration
Large operating air gaps
Operation with supply voltages down to 3.3 V
Digital output representing target profile
Single-chip solution for high reliability
Optimized Hall IC/magnet system
Continued on the next page…
Packages: 4 pin SIP (suffix SE)
Description
Recognizing the increasingly stringent requirements for EMC/
EMI in automotive applications,Allegro has taken the necessary
steps to design devices that are capable of withstanding the
effects of radiated and conducted transients. The ATS673
and ATS674 devices have been designed specifically for this
purpose. Advanced circuitry on the die allows them to survive
positive and negative transient pulses on both the input and
output.
The ATS673 and ATS674 devices retain all of the same
characteristics as theATS671 andATS672. The devices remain
true zero-speed gear tooth sensors with optimized Hall IC/
magnet configuration in an SIP (single in-line package). The
SIP assembly consists of a molded package that holds together
a samarium cobalt magnet, a pole piece, and a true zero-speed
Hall IC that has been optimized to the magnetic circuit.
The sensor incorporates a single element Hall IC that switches
in response to magnetic signals created by a ferrous target.
The IC contains a sophisticated digital circuit designed
to eliminate the detrimental effects of magnet and system
offsets.www.DataSheet4U.com Signal processing is used to provide zero-speed
Not to scale
ATS673-DS, Rev. 1
Continued on the next page…
V+
VCC
0.1 μF
CBYPASS
Functional Block Diagram
Hall
Amp
Voltage
Regulator
(Analog)
VREG(A)
Voltage
Regulator
(Digital)
VREG(D)
Offset Adjust
Temperature
Coefficient
Adjust
LPF
Automatic
Gain
Control
VPROC
Offset TC
VREF
Comp_P
Clock
Continuous
Update Logic
Output State
Clock
Continuous
Update Logic
Comp_N
Output State
9-Bit
PDAC
9
9-Bit
Counter
9-Bit
Counter
9
9-Bit
NDAC
Threshold
Output
TPOS
VREG(A)
Power-On
Reset
TPOS Trim
GND
(Recommended)
TEST
VREG(D)
Output
Driver
Threshold
Comparator
VOUT

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