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PDF NB4L52 Data sheet ( Hoja de datos )
| Número de pieza | NB4L52 | |
| Descripción | Differential Data/Clock D Flip-Flop | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NB4L52
2.5 V/3.3 V/5.0 V Differential
Data/Clock D Flip-Flop
with Reset
Multi−Level Inputs to LVPECL Translator
w/ Internal Termination
The NB4L52 is a differential Data and Clock D flip−flop with a
differential asynchronous Reset. The differential inputs incorporate
internal 50 W termination resistors and will accept PECL, LVPECL,
LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock
transitions from Low to High, Data will be transferred to the
differential LVPECL outputs. The differential Clock inputs allow the
NB4L52 to also be used as a negative edge triggered device. The
device is housed in a small 3x3 mm 16 pin QFN package.
Features
• Maximum Input Clock Frequency > 4 GHz Typical
• 330 ps Typical Propagation Delay
• 145 ps Typical Rise and Fall Times
• Differential LVPECL Outputs, 750 mV Peak−to−Peak, Typical
• Operating Range: VCC = 2.375 V to 5.5 V with VEE = 0 V
• Internal Input Termination Resistors, 50 W
• Functionally Compatible with Existing 2.5 V/3.3 V/5.0 V LVEL,
LVEP, EP, and SG Devices
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
http://onsemi.com
1
QFN−16
MN SUFFIX
CASE 485G
MARKING DIAGRAM*
16
1
NB4L
52
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VTD
D
D
VTD
VTCLK
CLK
CLK
VTCLK
Data
Clock
Reset
Q
Q
© Semiconductor Components Industries, LLC, 2009
August, 2009 − Rev. 3
VTR R R VTR
Figure 1. Logic Diagram
Table 1. TRUTH TABLE
R D CLK
Hx
x
LL
LH
Z
Z
Z = LOW to HIGH Transition
x = Don’t Care
Q
L
L
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
1 Publication Order Number:
NB4L52/D
1 page  
NB4L52
Table 6. AC CHARACTERISTICS VCC = 2.375 V to 5.5 V; VEE = 0 V or VCC = 0 V, VEE = −2.375 to −5.5 V (Note 8)
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
VOUTPP
tPLH,
tPHL
ts
th
tRR
tPW
tJITTER
VINPP
Output Voltage Amplitude (@ VINPPmin)
(Note 10) (See Figure 4)
fin v 2.0 GHz
fin v 3.0 GHz
fin v 4.0 GHz
Propagation Delay to
Output Differential
CLK to Q, R to Q
Setup Time
Hold Time
Reset Recovery
Minimum Pulse Width
R/R
RMS Random Clock Jitter (Note 9)
fin v 2.0 GHz
fin v 3.0 GHz
fin v 4.0 GHz
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)
530
490
380
300
100
50
400
250
150
770 530
720 490
580 380
400 500 300
100
50
400
250
1
1
1
2800 150
780 530
730 490
580 380
400 500 300
100
50
400
250
1
1
1
2800 150
mV
760
680
530
400 500 ps
ps
ps
ps
ps
ps
1
1
1
2800 mV
tr Output Rise/Fall Times @ 0.5 GHz
tf (20% − 80%)
80 135 190 80 145 190 80 155 190 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
8. Mraeteassu4r0epdsb(y2f0o%rci−ng80V%IN)P.P (MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC – 2.0 V. Input edge
9. Additive RMS jitter with 50% duty cycle clock signal.
10. Input and output voltage swing is a single−ended measurement operating in differential mode.
800
700
600
500
400
300
200
100
0
01 2 3
fin, CLOCK INPUT FREQUENCY (GHz)
4
Figure 3. Output Voltage Amplitude (VOUTPP) vs.
Clock Input Frequency at Ambient Temperature (Typical).
http://onsemi.com
5
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| PDF Descargar | [ Datasheet NB4L52.PDF ] | |
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