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PDF AT32AP7002 Data sheet ( Hoja de datos )
| Número de pieza | AT32AP7002 | |
| Descripción | 32-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• High Performance, Low Power AVR®32 32-Bit Microcontroller
– 210 DMIPS throughput at 150 MHz
– 16 KB instruction cache and 16 KB data caches
– Memory Management Unit enabling use of operating systems
– Single-cycle RISC instruction set including SIMD and DSP instructions
– Java Hardware Acceleration
• Multimedia Co-Processor
– Vector Multiplication Unit for video acceleration through color-space conversion
(YUV<->RGB), image scaling and filtering, quarter pixel motion compensation
• Multi-hierarchy bus system
– High-performance data transfers on separate buses for increased performance
• Data Memories
– 32KBytes SRAM
• External Memory Interface
– SDRAM, DataFlash™, SRAM, Multi Media Card (MMC), Secure Digital (SD),
– Compact Flash, Smart Media, NAND Flash
• Direct Memory Access Controller
– External Memory access without CPU intervention
• Interrupt Controller
– Individually maskable Interrupts
– Each interrupt request has a programmable priority and autovector address
• System Functions
– Power and Clock Manager
– Crystal Oscillator with Phase-Lock-Loop (PLL)
– Watchdog Timer
– Real-time Clock
• 6 Multifunction timer/counters
– Three external clock inputs, I/O pins, PWM, capture and various counting
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capabilities
• 4 Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
– 115.2 kbps IrDA Modulation and Demodulation
– Hardware and software handshaking
• 3 Synchronous Serial Protocol controllers
– Supports I2S, SPI and generic frame-based protocols
• Two-Wire Interface
– Sequential Read/Write Operations, Philips’ I2C© compatible
• Liquid Crystal Display (LCD) interface
– Supports TFT displays
– Configurable pixel resolution supporting QCIF/QVGA/VGA/SVGA configurations.
• Image Sensor Interface
– 12-bit Data Interface for CMOS cameras
• Universal Serial Bus (USB) 2.0 High Speed (480 Mbps) Device
– On-chip Transceivers with physical interface
• 16-bit stereo audio DAC
– Sample rates up to 50 kHz
• On-Chip Debug System
– Nexus Class 3
– Full speed, non-intrusive data and program trace
– Runtime control and JTAG interface
• Package/Pins
– AT32AP7002: 196-ball CTBGA
• Power supplies
– 1.65V to1.95V VDDCORE
– 3.0V to 3.6V VDDIO
AVR®32 32-bit
Microcontroller
AT32AP7002
Preliminary
Summary
32054AS-AVR32-02/07
1 page  
AT32AP7002
2.1 Processor and architecture
2.1.1 AVR32AP CPU
• 32-bit load/store AVR32B RISC architecture.
– Up to 15 general-purpose 32-bit registers.
– 32-bit Stack Pointer, Program Counter and Link Register reside in register file.
– Fully orthogonal instruction set.
– Privileged and unprivileged modes enabling efficient and secure Operating Systems.
– Innovative instruction set together with variable instruction length ensuring industry leading
code density.
– DSP extention with saturating arithmetic, and a wide variety of multiply instructions.
– SIMD extention for media applications.
• 7 stage pipeline allows one instruction per clock cycle for most instructions.
– Java Hardware Acceleration.
– Byte, half-word, word and double word memory access.
– Unaligned memory access.
– Shadowed interrupt context for INT3 and multiple interrupt priority levels.
– Dynamic branch prediction and return address stack for fast change-of-flow.
– Coprocessor interface.
• Full MMU allows for operating systems with memory protection.
• 16Kbyte Instruction and 16Kbyte data caches.
– Virtually indexed, physically tagged.
– 4-way associative.
– Write-through or write-back.
• Nexus Class 3 On-Chip Debug system.
– Low-cost NanoTrace supported.
2.1.2
Pixel Coprocessor (PiCo)
• Coprocessor coupled to the AVR32 CPU Core through the TCB Bus.
• Three parallel Vector Multiplication Units (VMU) where each unit can:
– Multiply three pixel components with three coefficients.
– Add the products from the multiplications together.
– Accumulate the result or add an offset to the sum of the products.
• Can be used for accelerating:
– Image Color Space Conversion.
• Configurable Conversion Coefficients.
• Supports packed and planar input and output formats.
• Supports subsampled input color spaces (i.e 4:2:2, 4:2:0).
– Image filtering/scaling.
• Configurable Filter Coefficients.
• Throughput of one sample per cycle for a 9-tap FIR filter.
• Can use the built-in accumulator to extend the FIR filter to more than 9-taps.
• Can be used for bilinear/bicubic interpolations.
– MPEG-4/H.264 Quarter Pixel Motion Compensation.
• Flexible input Pixel Selector.
– Can operate on numerous different image storage formats.
• Flexible Output Pixel Inserter.
– Scales and saturates the results back to 8-bit pixel values.
32054AS–AVR32–02/07
5
5 Page 
AT32AP7002
Table 3-1. Signal Description List
Signal Name
EVTO_N
GCLK0 - GCLK4
OSCEN_N
RESET_N
WAKE_N
EXTINT0 - EXTINT3
NMI_N
SCLK
SDI
SDO
SYNC
DATA0 - DATA1
DATAN0 - DATAN1
ADDR0 - ADDR25
CAS
CFCE1
CFCE2
CFRNW
DATA0 - DATA31
NANDOE
NANDWE
NCS0 - NCS5
NRD
Function
Type
Event Out
Output
Power Manager - PM
Generic Clock Pins
Output
Oscillator Enable
Input
Reset Pin
Input
Wake Pin
Input
External Interrupt Module - EIM
External Interrupt Pins
Input
Non-Maskable Interrupt Pin
Input
AC97 Controller - AC97C
AC97 Clock Signal
Input
AC97 Receive Signal
Output
AC97 Transmit Signal
Output
AC97 Frame Synchronization Signal
Input
DAC - DAC
D/A Data Out
Output
D/A Inverted Data Out
Output
External Bus Interface - EBI
Address Bus
Output
Column Signal
Output
Compact Flash 1 Chip Enable
Output
Compact Flash 2 Chip Enable
Output
Compact Flash Read Not Write
Output
Data Bus
I/O
NAND Flash Output Enable
Output
NAND Flash Write Enable
Output
Chip Select
Output
Read Signal
Output
Active
Level Comments
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
32054AS-AVR32-02/07
11
11 Page | ||
| Páginas | Total 45 Páginas | |
| PDF Descargar | [ Datasheet AT32AP7002.PDF ] | |
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