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PDF AT45DB011B Data sheet ( Hoja de datos )
| Número de pieza | AT45DB011B | |
| Descripción | 1-megabit 2.7-volt Only DataFlash | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Single 2.7V - 3.6V Supply
• Serial Peripheral Interface (SPI) Compatible
• 20 MHz Max Clock Frequency
• Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 512 Pages (264 Bytes/Page) Main Memory
• Supports Page and Block Erase Operations
• One 264-byte SRAM Data Buffer
• Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
• Fast Page Program Time – 7 ms Typical
• 120 µs Typical Page to Buffer Transfer Time
• Low Power Dissipation
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
• Hardware Data Protection Feature
• 100% Compatible with AT45DB011
• Commercial and Industrial Temperature Ranges
• Green (Pb/Halide-free/RoHS Compliant) Packaging Options
1-megabit
2.7-volt Only
DataFlash®
AT45DB011B
Description
The AT45DB011B is a 2.7-volt only, serial interface Flash memory ideally suited for
a wide variety of digital voice-, image-, program code- and data-storage applications.
Its 1,081,344 bits of memory are organized as 512 pages of 264 bytes each. In addi-
tion to the main memory, the AT45DB011B also contains one SRAM data buffer of 264
bytes. The buffer allows receiving of data while a page in the main memory is being
reprogrammed. EEPROM emulation (bit or byte alterawbwiwl.iDtayta)Shieset4Ue.caomsily handled with a
self-contained three step Read-Modify-Write operation. Unlike conventional Flash
memories that are accessed randomly with multiple address lines and a parallel inter-
face, the DataFlash uses a SPI serial interface to sequentially access its data. SPI
mode 0 and mode 3 are supported. The simple serial interface facilitates hardware
Pin Configurations
Pin Name
CS
SCK
SI
SO
WP
RESET
RDY/BUSY
Function
Chip Select
Serial Clock
Serial Input
Serial Output
Hardware Page
Write Protect Pin
Chip Reset
Ready/Busy
SOIC
SI
SCK
RESET
CS
1
2
3
4
8 SO
7 GND
6 VCC
5 WP
CBGA Top View
through Package
123
A
SCK GND VCC
B
CS RDY/BSY WP
C
SO SI RESET
TSSOP Top View
Type 1
RDY/BUSY
RESET
WP
VCC
GND
SCK
SO
1
2
3
4
5
6
7
14 CS
13 NC
12 NC
11 NC
10 NC
9 NC
8 SI
AT45DB011B
Preliminary 16-
Megabit 2.7-volt
Only Serial
DataFlash
1984J–DFLASH–06/06
1
1 page  
AT45DB011B
Program and
Erase Commands
STATUS REGISTER READ: The status register can be used to determine the device’s
ready/busy status, the result of a Main Memory Page to Buffer Compare operation, or the
device density. To read the status register, an opcode of 57H or D7H must be loaded into the
device. After the last bit of the opcode is shifted in, the eight bits of the status register, starting
with the MSB (bit 7), will be shifted out on the SO pin during the next eight clock cycles. The
five most significant bits of the status register will contain device information, while the remain-
ing three least significant bits are reserved for future use and will have undefined values. After
bit 0 of the status register has been shifted out, the sequence will repeat itself (as long as CS
remains low and SCK is being toggled) starting again with bit 7. The data in the status register
is constantly updated, so each repeating sequence will output new data.
Status Register Format
Bit 7
RDY/BUSY
Bit 6
COMP
Bit 5
0
Bit 4
0
Bit 3
1
Bit 2
1
Bit 1
X
Bit 0
X
Ready/Busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device
is not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy
state. The user can continuously poll bit 7 of the status register by stopping SCK at a low level
once bit 7 has been output. The status of bit 7 will continue to be output on the SO pin, and
once the device is no longer busy, the state of SO will change from 0 to 1. There are eight
operations which can cause the device to be in a busy state: Main Memory Page to Buffer
Transfer, Main Memory Page to Buffer Compare, Buffer to Main Memory Page Program with
Built-in Erase, Buffer to Main Memory Page Program without Built-in Erase, Page Erase,
Block Erase, Main Memory Page Program, and Auto Page Rewrite.
The result of the most recent Main Memory Page to Buffer Compare operation is indicated
using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches
the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page
does not match the data in the buffer.
The device density is indicated using bits 5, 4, 3 and 2 of the status register. For the
AT45DB011B, the four bits are 0, 0, 1 and 1. The decimal value of these four binary bits does
not equate to the device density; the three bits represent a combinational code relating to dif-
fering densities of Serial DataFlash devices, allowing a total of sixteen different density
configurations.
BUFFER WRITE: Data can be shifted in from the SI pin into the data buffer. To load data into
the buffer, an 8-bit opcode of 84H is followed by 15 don’t care bits and nine address bits
(BFA8-BFA0). The nine address bits specify the first byte in the buffer to be written. The data
is entered following the address bits. If the end of the data buffer is reached, the device will
wrap around back to the beginning of the buffer. Data will continue to be loaded into the buffer
until a low-to-high transition is detected on the CS pin.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN ERASE: Data written into
the buffer can be programmed into the main memory. An 8-bit opcode of 83H is followed by
the six reserved bits, nine address bits (PA8-PA0) that specify the page in the main memory
to be written, and nine additional don’t care bits. When a low-to-high transition occurs on the
CS pin, the part will first erase the selected page in main memory to all 1s and then program
the data stored in the buffer into the specified page in the main memory. Both the erase and
the programming of the page are internally self-timed and should take place in a maximum
time of tEP. During this time, the status register will indicate that the part is busy.
1984J–DFLASH–06/06
5
5 Page 
AT45DB011B
Table 1. Read Commands
Command
Continuous Array Read
Main Memory Page Read
Buffer Read
Status Register Read
SCK Mode
Inactive Clock Polarity Low or High
SPI Mode 0 or 3
Inactive Clock Polarity Low or High
SPI Mode 0 or 3
Inactive Clock Polarity Low or High
SPI Mode 0 or 3
Inactive Clock Polarity Low or High
SPI Mode 0 or 3
Opcode
68H
E8H
52H
D2H
54H
D4H
57H
D7H
Table 2. Program and Erase Commands
Command
Buffer Write
Buffer to Main Memory Page Program with Built-in Erase
Buffer to Main Memory Page Program without Built-in Erase
Page Erase
Block Erase
Main Memory Page Program through Buffer
SCK Mode
Any
Any
Any
Any
Any
Any
Opcode
84H
83H
88H
81H
50H
82H
Table 3. Additional Commands
Command
Main Memory Page to Buffer Transfer
Main Memory Page to Buffer Compare
Auto Page Rewrite through Buffer
SCK Mode
Any
Any
Any
Opcode
53H
60H
58H
Note: In Tables 2 and 3, an SCK mode designation of “Any” denotes any one of the four modes of operation (Inactive Clock Polarity
Low, Inactive Clock Polarity High, SPI Mode 0, or SPI Mode 3).
1984J–DFLASH–06/06
11
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| PDF Descargar | [ Datasheet AT45DB011B.PDF ] | |
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