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PDF AT45DB021D Data sheet ( Hoja de datos )
| Número de pieza | AT45DB021D | |
| Descripción | 2-megabit 2.7-volt DataFlash | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Single 2.7V to 3.6V Supply
• RapidS® Serial Interface: 66 MHz Maximum Clock Frequency
– SPI Compatible Modes 0 and 3
• User Configurable Page Size
– 256 Bytes per Page
– 264 Bytes per Page
• Page Program Operation
– Intelligent Programming Operation
– 1,024 Pages (256/264 Bytes/Page) Main Memory
• Flexible Erase Options
– Page Erase (256 Bytes)
– Block Erase (2 Kbytes)
– Sector Erase (32 Kbytes)
– Chip Erase (2 Mbits)
• One SRAM Data Buffer (256/264 Bytes)
• Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
• Low-power Dissipation
– 7 mA Active Read Current Typical
– 25 µA Standby Current Typical
– 5 µA Deep Power-down Typical
• Hardware and Software Data Protection Features
– Individual Sector
• Sector Lockdown for Secure Code and Data Storage
www.DataSheet4U.com
– Individual Sector
• Security: 128-byte Security Register
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
• JEDEC Standard Manufacturer and Device ID Read
• 100,000 Program/Erase Cycles Per Page Minimum
• Data Retention – 20 Years
• Industrial Temperature Range
• Green (Pb/Halide-free/RoHS Compliant) Packaging Options
2-megabit
2.7-volt
DataFlash
AT45DB021D
Preliminary
1. Description
The AT45DB021D is a 2.7V, serial-interface Flash memory ideally suited for a wide
variety of digital voice-, image-, program code- and data-storage applications. The
AT45DB021D supports RapidS serial interface for applications requiring very high
speed operations. RapidS serial interface is SPI compatible for frequencies up to 66
MHz. Its 2,162,688 bits of memory are organized as 1,024 pages of 256 bytes or 264
bytes each. In addition to the main memory, the AT45DB021D also contains one
SRAM buffer of 256/264 bytes. EEPROM emulation (bit or byte alterability) is easily
handled with a self-contained three step read-modify-write operation. Unlike conven-
tional Flash memories that are accessed randomly with multiple address lines and a
parallel interface, the DataFlash® uses a RapidS serial interface to sequentially
access its data. The simple sequential access dramatically reduces active pin count,
facilitates hardware layout, increases system reliability, minimizes switching noise,
and reduces package size.
3638B–DFLASH–02/07
1 page  
AT45DB021D [Preliminary]
6. Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from the
SRAM data buffer. The DataFlash supports RapidS protocols for Mode 0 and Mode 3. Please
refer to the “Detailed Bit-level Read Timing” diagrams in this datasheet for details on the clock
cycle sequences for each mode.
6.1 Continuous Array Read (Legacy Command – E8H): Up to 66 MHz
By supplying an initial starting address for the main memory array, the Continuous Array Read
command can be utilized to sequentially read a continuous stream of data from the device by
simply providing a clock signal; no additional addressing information or control signals need to
be provided. The DataFlash incorporates an internal address counter that will automatically
increment on every clock cycle, allowing one continuous read operation without the need of
additional address sequences. To perform a continuous read from the DataFlash standard page
size (264 bytes), an opcode of E8H must be clocked into the device followed by three address
bytes (which comprise the 24-bit page and byte address sequence) and 4 don’t care bytes. The
first 10 bits (PA9 - PA0) of the 19-bit address sequence specify which page of the main memory
array to read, and the last 9 bits (BA8 - BA0) of the 19-bit address sequence specify the starting
byte address within the page. To perform a continuous read from the binary page size (256
bytes), the opcode (E8H) must be clocked into the device followed by three address bytes and 4
don’t care bytes. The first 10 bits (A17 - A8) of the 18-bits sequence specify which page of the
main memory array to read, and the last 8 bits (A7 - A0) of the 18-bits address sequence specify
the starting byte address within the page. The don’t care bytes that follow the address bytes are
needed to initialize the read operation. Following the don’t care bytes, additional clock pulses on
the SCK pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care
bytes, and the reading of data. When the end of a page in main memory is reached during a
Continuous Array Read, the device will continue reading at the beginning of the next page with
no delays incurred during the page boundary crossover (the crossover from the end of one page
to the beginning of the next page). When the last bit in the main memory array has been read,
the device will continue reading back at the beginning of the first page of memory. As with cross-
ing over page boundaries, no delays will be incurred when wrapping around from the end of the
array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output
pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by
the fCAR1 specification. The Continuous Array Read bypasses the data buffer and leaves the
contents of the buffer unchanged.
6.2 Continuous Array Read (High Frequency Mode – 0BH): Up to 66 MHz
This command can be used with the serial interface to read the main memory array sequentially
in high speed mode for any clock frequency up to the maximum specified by fCAR1. To perform a
continuous read array with the page size set to 264 bytes, the CS must first be asserted then an
opcode 0BH must be clocked into the device followed by three address bytes and a dummy
byte. The first 10 bits (PA9 - PA0) of the 19-bit address sequence specify which page of the
main memory array to read, and the last 9 bits (BA8 - BA0) of the 19-bit address sequence spec-
ify the starting byte address within the page. To perform a continuous read with the page size
set to 256 bytes, the opcode, 0BH, must be clocked into the device followed by three address
bytes (A17 - A0) and a dummy byte. Following the dummy byte, additional clock pulses on the
SCK pin will result in data being output on the SO (serial output) pin.
3638B–DFLASH–02/07
5
5 Page 
AT45DB021D [Preliminary]
7.8 Main Memory Page Program Through Buffer
This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program
with Built-in Erase operations. Data is first clocked into the buffer from the input pin (SI) and then
programmed into a specified page in the main memory. To perform a main memory page pro-
gram through buffer for the DataFlash standard page size (264 bytes), a 1-byte opcode, 82H,
must first be clocked into the device, followed by three address bytes. The address bytes are
comprised of 5 don’t care bits, 10 page address bits, (PA9 - PA0) that select the page in the
main memory where data is to be written, and 9 buffer address bits (BFA8 - BFA0) that select
the first byte in the buffer to be written. To perform a main memory page program through buffer
for the binary page size (256 bytes), the opcode 82H must be clocked into the device followed
by three address bytes consisting of 6 don’t care bits, 10 page address bits (A17 - A8) that spec-
ify the page in the main memory to be written, and 8 buffer address bits (BFA7 - BFA0) that
selects the first byte in the buffer to be written. After all address bytes are clocked in, the part will
take data from the input pins and store it in the specified data buffer. If the end of the buffer is
reached, the device will wrap around back to the beginning of the buffer. When there is a low-to-
high transition on the CS pin, the part will first erase the selected page in main memory to all 1s
and then program the data stored in the buffer into that memory page. Both the erase and the
programming of the page are internally self-timed and should take place in a maximum time of
tEP. During this time, the status register will indicate that the part is busy.
8. Sector Protection
Two protection methods, hardware and software controlled, are provided for protection against
inadvertent or erroneous program and erase cycles. The software controlled method relies on
the use of software commands to enable and disable sector protection while the hardware con-
trolled method employs the use of the Write Protect (WP) pin. The selection of which sectors
that are to be protected or unprotected against program and erase operations is specified in the
nonvolatile Sector Protection Register. The status of whether or not sector protection has been
enabled or disabled by either the software or the hardware controlled methods can be deter-
mined by checking the Status Register.
3638B–DFLASH–02/07
11
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| PDF Descargar | [ Datasheet AT45DB021D.PDF ] | |
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