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PDF AT45DB081D Data sheet ( Hoja de datos )
| Número de pieza | AT45DB081D | |
| Descripción | 8-megabit 2.5-volt or 2.7-volt DataFlash | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Single 2.5V or 2.7V to 3.6V Supply
• RapidS® Serial Interface: 66 MHz Maximum Clock Frequency
– SPI Compatible Modes 0 and 3
• User Configurable Page Size
– 256 Bytes per Page
– 264 Bytes per Page
• Page Program Operation
– Intelligent Programming Operation
– 4,096 Pages (256/264 Bytes/Page) Main Memory
• Flexible Erase Options
– Page Erase (256 Bytes)
– Block Erase (2 Kbytes)
– Sector Erase (64 Kbytes)
– Chip Erase (8 Mbits)
• Two SRAM Data Buffers (256/264 Bytes)
– Allows Receiving of Data while Reprogramming the Flash Array
• Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
• Low-power Dissipation
– 7 mA Active Read Current Typical
– 25 µA Standby Current Typical
– 5 µA Deep Power Down Typical
• Hardware and Software Data Protection Features
– Individual Sector
www.DataSheet4U.com
• Sector Lockdown for Secure Code and Data Storage
– Individual Sector
• Security: 128-byte Security Register
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
• JEDEC Standard Manufacturer and Device ID Read
• 100,000 Program/Erase Cycles Per Page Minimum
• Data Retention – 20 Years
• Industrial Temperature Range
• Green (Pb/Halide-free/RoHS Compliant) Packaging Options
8-megabit
2.5-volt or
2.7-volt
DataFlash®
AT45DB081D
1. Description
The AT45DB081D is a 2.5V or 2.7V, serial-interface Flash memory ideally suited for a
wide variety of digital voice-, image-, program code- and data-storage applications.
The AT45DB081D supports RapidS serial interface for applications requiring very
high speed operations. RapidS serial interface is SPI compatible for frequencies up to
66 MHz. Its 8,650,752 bits of memory are organized as 4,096 pages of 256 bytes or
264 bytes each. In addition to the main memory, the AT45DB081D also contains two
SRAM buffers of 256/264 bytes each. The buffers allow the receiving of data while a
page in the main Memory is being reprogrammed, as well as writing a continuous
data stream. EEPROM emulation (bit or byte alterability) is easily handled with a self-
contained three step read-modify-write operation. Unlike conventional Flash memo-
ries that are accessed randomly with multiple address lines and a parallel interface,
3596E–DFLASH–02/07
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AT45DB081D
5. Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions
and their associated opcodes are contained in Table 15-1 on page 28 through Table 15-7 on
page 31. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit
opcode and the desired buffer or main memory address location. While the CS pin is low, tog-
gling the SCK pin controls the loading of the opcode and the desired buffer or main memory
address location through the SI (serial input) pin. All instructions, addresses, and data are trans-
ferred with the most significant bit (MSB) first.
Buffer addressing for the DataFlash standard page size (264 bytes) is referenced in the
datasheet using the terminology BFA8 - BFA0 to denote the 9 address bits required to designate
a byte address within a buffer. Main memory addressing is referenced using the terminology
PA11 - PA0 and BA8 - BA0, where PA11 - PA0 denotes the 12 address bits required to desig-
nate a page address and BA8 - BA0 denotes the 9 address bits required to designate a byte
address within the page.
For “Power of 2” binary page size (256 bytes) the Buffer addressing is referenced in the
datasheet using the conventional terminology BFA7 - BFA0 to denote the 8 address bits
required to designate a byte address within a buffer. Main memory addressing is referenced
using the terminology A19 - A0, where A19 - A8 denotes the 12 address bits required to desig-
nate a page address and A7 - A0 denotes the 8 address bits required to designate a byte
address within a page.
6. Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from either
one of the two SRAM data buffers. The DataFlash supports RapidS protocols for Mode 0 and
Mode 3. Please refer to the “Detailed Bit-level Read Timing” diagrams in this datasheet for
details on the clock cycle sequences for each mode.
6.1 Continuous Array Read (Legacy Command: E8H): Up to 66 MHz
By supplying an initial starting address for the main memory array, the Continuous Array Read
command can be utilized to sequentially read a continuous stream of data from the device by
simply providing a clock signal; no additional addressing information or control signals need to
be provided. The DataFlash incorporates an internal address counter that will automatically
increment on every clock cycle, allowing one continuous read operation without the need of
additional address sequences. To perform a continuous read from the DataFlash standard page
size (264 bytes), an opcode of E8H must be clocked into the device followed by three address
bytes (which comprise the 24-bit page and byte address sequence) and 4 don’t care bytes. The
first 12 bits (PA11 - PA0) of the 21-bit address sequence specify which page of the main mem-
ory array to read, and the last 9 bits (BA8 - BA0) of the 21-bit address sequence specify the
starting byte address within the page. To perform a continuous read from the binary page size
(256 bytes), the opcode (E8H) must be clocked into the device followed by three address bytes
and 4 don’t care bytes. The first 12 bits (A19 - A8) of the 20-bits sequence specify which page of
the main memory array to read, and the last 8 bits (A7 - A0) of the 20-bits address sequence
specify the starting byte address within the page. The don’t care bytes that follow the address
bytes are needed to initialize the read operation. Following the don’t care bytes, additional clock
pulses on the SCK pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care
bytes, and the reading of data. When the end of a page in main memory is reached during a
3596E–DFLASH–02/07
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AT45DB081D
The WP pin can be asserted while the device is erasing, but protection will not be activated until
the internal erase cycle completes.
Command
Chip Erase
Byte 1
C7H
Byte 2
94H
Byte 3
80H
Byte 4
9AH
Figure 7-1. Chip Erase
CS
SI
Opcode
Byte 1
Each transition
represents 8 bits
Opcode
Byte 2
Opcode
Byte 3
Opcode
Byte 4
Note: Refer to errata regarding Chip Erase on page 52.
7.8 Main Memory Page Program Through Buffer
This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program
with Built-in Erase operations. Data is first clocked into buffer 1 or buffer 2 from the input pin (SI)
and then programmed into a specified page in the main memory. To perform a main memory
page program through buffer for the DataFlash standard page size (264 bytes), a 1-byte opcode,
82H for buffer 1 or 85H for buffer 2, must first be clocked into the device, followed by three
address bytes. The address bytes are comprised of 3 don’t care bits, 12 page address bits,
(PA11 - PA0) that select the page in the main memory where data is to be written, and 9 buffer
address bits (BFA8 - BFA0) that select the first byte in the buffer to be written. To perform a
main memory page program through buffer for the binary page size (256 bytes), the opcode 82H
for buffer 1 or 85H for buffer 2, must be clocked into the device followed by three address bytes
consisting of 4 don’t care bits, 12 page address bits (A19 - A8) that specify the page in the main
memory to be written, and 8 buffer address bits (BFA7 - BFA0) that selects the first byte in the
buffer to be written. After all address bytes are clocked in, the part will take data from the input
pins and store it in the specified data buffer. If the end of the buffer is reached, the device will
wrap around back to the beginning of the buffer. When there is a low-to-high transition on the CS
pin, the part will first erase the selected page in main memory to all 1s and then program the
data stored in the buffer into that memory page. Both the erase and the programming of the
page are internally self-timed and should take place in a maximum time of tEP. During this time,
the status register will indicate that the part is busy.
8. Sector Protection
Two protection methods, hardware and software controlled, are provided for protection against
inadvertent or erroneous program and erase cycles. The software controlled method relies on
the use of software commands to enable and disable sector protection while the hardware con-
trolled method employs the use of the Write Protect (WP) pin. The selection of which sectors
that are to be protected or unprotected against program and erase operations is specified in the
nonvolatile Sector Protection Register. The status of whether or not sector protection has been
enabled or disabled by either the software or the hardware controlled methods can be deter-
mined by checking the Status Register.
3596E–DFLASH–02/07
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| PDF Descargar | [ Datasheet AT45DB081D.PDF ] | |
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