|
|
PDF Z5380 Data sheet ( Hoja de datos )
| Número de pieza | Z5380 | |
| Descripción | SMALL COMPUTER SYSTEM INTERFACE | |
| Fabricantes | Zilog | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de Z5380 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
ZILOG Z5380 SCSI
PRODUCT SPECIFICATION
FEATURES
Z5380 SCSI
SMALL COMPUTER
SYSTEM INTERFACE (SCSI)
s Pin Compatible with the Industry Standard 5380
s Supports Target and Initiator Roles
s 40-Pin DIP or 44-Pin PLCC Package Styles
s Arbitration Support
s Low-Power CMOS
s DMA or Programmed I/O Data Transfers
s Asynchronous Interface (Supports 1.5 MB/s)
s Supports Normal or Block Mode DMA
s Direct SCSI Bus Interface with On-Board 48 mA Drivers s Memory or I/O Mapped CPU Interface
GENERAL DESCRIPTION
The Z5380 SCSI (Small Computer System Interface) con- detects a bus condition that requires attention. It also
troller is designed to implement the SCSI protocol as supports arbitration and reselection. The Z5380 has the
defined by the ANSI X3.131-1986 standard, and is fwuwwll.DyataSheetp4Ur.coomper hand-shake signals to support normal and block
compatible with the industry standard 5380. It is capable mode DMA operations with most DMA controllers avail-
of operating both as a Target and as an Initiator. Special able (Figure 2).
high-current open-drain outputs enable the Z5380 to di-
rectly interface to, and drive, the SCSI bus. The Z5380 has Notes:
the necessary interface hook-ups which allows the system
CPU to communicate with it like any other peripheral
All Signals with a preceding front slash, "/", are active Low, e.g.,
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
device. The CPU can read from, or write to, the SCSI
registers which are addressed as standard or memory- Power connections follow conventional descriptions below:
mapped I/Os (Figure 1).
Connection
Circuit
Device
The Z5380 increases the system performance by minimiz-
ing the CPU intervention in DMA operations which the SCSI
controls. The CPU is interrupted by the SCSI when it
Power
Ground
VCC
GND
VDD
VSS
PS97SCC0100
PS009101-0201
1
1 page  
ZILOG Z5380 SCSI
Table 1. Register Summary
Address
A2 A1 A0 R/W
Register Name
000R
Current SCSI Data
0 0 0W
Output Data
0 0 1 R/W Initiator Command
0 1 0 R/W Mode
0 1 1 R/W Target Command
100R
Current SCSI Bus Status
1 0 0W
Select Enable
101R
Bus and Status
1 0 1W
110R
1 1 0W
111R
1 1 1W
Start DMA Send
Input Data
Start DMA Target Receive
Reset Parity/Interrupt
Start DMA Initiator Receive
Data Registers
Address: 0
(Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
/DB0
/DB1
/DB2
/DB3
/DB4
/DB5
/DB6
/DB7
Figure 4. Current SCSI Data Register
Address: 0
(Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
The data registers are used to transfer SCSI commands,
data, status, and message bytes between the micropro-
cessor Data Bus and the SCSI Bus. The Z5380 does not
interpret any information that passes through the data
registers. The data registers consist of the transparent
Current SCSI Data Register, the Output Data Register, and
the Input Data Register.
Current SCSI Data Register. Address 0 (Read Only). The
Current SCSI Data Register (Figure 4) is a read-only
register which allows the microprocessor to read the active
SCSI Data Bus. This is accomplished by activating /CS
with an address on A2-A0 of 000 and issuing an /IOR pulse.
If parity checking is enabled, the SCSI Bus parity is
checked at the beginning of the read cycle. This register
is used during a programmed I/O data read or during
Arbitration to check for higher priority arbitrating devices.
Parity is not guaranteed valid during Arbitration.
Output Data Register. Address 0 (Write Only). The Output
Data Register (Figure 5) is a write-only register that is used
to send data to the SCSI Bus. This is accomplished by
either using a normal CPU write, or under DMA control, by
using /IOW and /DACK. This register also asserts the
proper ID bits on the SCSI Bus during the Arbitration and
Selection phases.
/DB0
/DB1
/DB2
/DB3
/DB4
/DB5
/DB6
/DB7
Figure 5. Output Data Register
Initiator Command Register. Address 1 (Read/Write).
The Initiator Command Register (Figures 6 and 7) are read
and write registers which assert certain SCSI Bus signals,
monitors those signals, and monitors the progress of bus
arbitration. Many of these bits are significant only when
being used as an Initiator; however, most can be used
during Target role operation.
PS97SCC0100
PS009101-0201
5
5 Page 
ZILOG
The proposed SCSI specification also requires that no
more than two device ID’s be active during the selection
process. To ensure this, the Current SCSI Data Register is
read.
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
14 and 15, respectively.
D7 D0
0 0 0 1X 0X 0
/ACK
/ATN
Busy Error
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
Z5380 SCSI
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register for this interrupt are
shown in Figures 16 and 17.
D7 D0
1 0 0 1 0 0 0X
/ACK
/ATN
Busy Error
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
Figure 16. Bus and Status Register
Figure 14. Bus and Status Register
D7 D0
0 0 0XXX 0X
/DBP
/SEL
I//O
C//D
/MSG
/REQ
/BSY
/RST
D7 D0
0 1 1XXX 0X
/DBP
/SEL
I//O
C//D
/MSG
/REQ
/BSY
/RST
Figure 17. Current SCSI Bus Status Register
Figure 15. Current SCSI Bus Status Register
End Of Process (EOP) Interrupt
An End Of Process signal (EOP) which occurs during a
DMA transfer (DMA Mode True) will set the End of DMA
Status bit (bit 7) and will optionally generate an interrupt if
Enable EOP Interrupt bit (Mode Register, bit 3) is True. The
/EOP pulse will not be recognized (End of DMA bit set)
unless /EOP, /DACK, and either /IOR or /IOW are concur-
rently active for at least 100 ns. DMA transfers can still
occur if /EOP was not asserted at the correct time. This
interrupt is disabled by resetting the Enable EOP Interrupt
bit.
The End of DMA bit is used to determine when a block
transfer is complete. Receive operations are complete
when there is no data left in the chip and no additional
handshakes occurring. The only exception to this is receiv-
ing data as an Initiator and the Target opts to send
additional data for the same phase. In this /REQ goes
active and the new data is present in the Input Data
Register. Since a phase-mismatch interrupt will not occur,
/REQ and /ACK need to be sampled to determine that the
Target is attempting to send more data.
PS97SCC0100
PS009101-0201
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet Z5380.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| Z5380 | SMALL COMPUTER SYSTEM INTERFACE | Zilog |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |