|
|
PDF AD9236 Data sheet ( Hoja de datos )
| Número de pieza | AD9236 | |
| Descripción | A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD9236 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Data Sheet
12-Bit, 80 MSPS, 3 V A/D Converter
AD9236
FEATURES
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 70.4 dBc to Nyquist
SFDR = 87.8 dBc to Nyquist
Low power: 366 mW
Differential input with 500 MHz bandwidth
On-chip reference and sample-and-hold
DNL = ±0.4 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
APPLICATIONS
High end medical imaging equipment
IF sampling in communications receivers
WCDMA, CDMA-One, CDMA-2000
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
DTV subsystems
GENERAL DESCRIPTION
The AD9236 is a monolithic, single 3 V supply, 12-bit, 80 MSPS
analog-to-digital converter featuring a high performance sample-
and-hold amplifier (SHA) and voltage reference. The AD9236
uses a multistage differential pipelined architecture with output
error correction logic to provide 12-bit accuracy at 80 MSPS
and guarantee no missing codes over the full operating
temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and common modes, including
single-ended applications. It is suitable for multiplexed systems
that switch full-scale voltage levels in successive channels and
for sampling single-channel inputs at frequencies well beyond
the Nyquist rate. Combined with power and cost savings over
previously available analog-to-digital converters, the AD9236 is
suitable for applications in communications, imaging, and
medical ultrasound.
A single-ended clock input is used to control all internal
conversion cycles. A duty cycle stabilizer (DCS) compensates
for wide variations in the clock duty cycle while maintaining
excellent overall ADC performance. The digital output data is
VIN+
VIN–
REFT
REFB
VREF
SENSE
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
AD9236
SHA
MDAC1
8-STAGE
1 1/2-BIT PIPELINE
A/D
4
A/D
16
3
REF
SELECT
CORRECTION LOGIC
12
OUTPUT BUFFERS
0.5V
CLOCK
DUTY CYCLE
STABILIZER
MODE
SELECT
OTR
D11 (MSB)
D0 (LSB)
AGND
CLK
Figure 1.
PDWN MODE DGND
03066-0-001
presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
can be used with the most significant bit to determine low or
high overflow. Fabricated on an advanced CMOS process, the
AD9236 is available in a 28-lead TSSOP and a 32-lead LFCSP
and is specified over the industrial temperature range
(−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9236 operates from a single 3 V power supply and
features a separate digital output driver supply to
accommodate 2.5 V and 3.3 V logic families.
2. Operating at 80 MSPS, the AD9236 consumes a low 366 mW.
3. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz, and can be configured for
single-ended or differential operation.
4. The AD9236 is pin compatible with the AD9215, AD9235,
and AD9245. This allows a simplified migration from 10 bits
to 14 bits and 20 MSPS to 80 MSPS.
5. The DCS maintains overall ADC performance over a wide
range of clock pulse widths.
6. The OTR output bit indicates when the signal is beyond the
selected input range.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, 1.0 V external reference, unless otherwise noted.
Table 3.
Parameter
LOGIC INPUTS (CLK, PDWN)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
DIGITAL OUTPUTS (D0–D11, OTR)1
DRVDD = 3.3 V
High Level Output Voltage (IOH = 50 µA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOH = 1.6 mA)
Low Level Output Voltage (IOH = 50 µA)
DRVDD = 2.5 V
High Level Output Voltage (IOH = 50 µA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOH = 1.6 mA)
Low Level Output Voltage (IOH = 50 µA)
1 Output voltage levels measured with 5 pF load on each output.
Temp
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
IV
V
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
AD9236
AD9236BRU/AD9236BCP
Min Typ Max
Unit
2.0
–10
–10
2
V
0.8 V
+10 µA
+10 µA
pF
3.29 V
3.25 V
0.2 V
0.05 V
2.49 V
2.45 V
0.2 V
0.05 V
Rev. C | Page 5 of 36
5 Page 
Data Sheet
AD9236
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.0 V, DRVDD = 2.5 V, sample rate = 80 MSPS, DCS disabled, TA = 25°C, 2 V p-p differential input, AIN = –0.5 dBFS,
VREF = 1.0 V external, unless otherwise noted.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
AIN = –0.5dBFS
SNR = 71.0dBc
ENOB = 11.5 BITS
SFDR = 93.6dBc
5 10 15 20 25 30
FREQUENCY (MHz)
Figure 9. Single Tone 8K FFT @ 2.5 MHz
35 40
03066-0-031
100
SFDR (dBFS)
90
SFDR (dBc)
80
SFDR = 90dB
REFERENCE LINE
70
SNR (dBFS)
60
SNR (dBc)
50
40
–30
–25 –20 –15 –10
INPUT AMPLITUDE (dBFS)
–5 0
03066-0-048
Figure 12. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 2.5 MHz
0
AIN = –0.5dBFS
–10 SNR = 70.6dBc
ENOB = 11.4 BITS
–20 SFDR = 87.8dBc
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5 10 15 20 25
FREQUENCY (MHz)
30
Figure 10. Single Tone 8K FFT @ 39 MHz
35 40
03066-0-032
100
SFDR (dBFS)
90
SFDR (dBc)
80
SFDR = 90dB
REFERENCE LINE
70
SNR (dBFS)
SNR (dBc)
60
50
40
–30
–25 –20 –15 –10
INPUT AMPLITUDE (dBFS)
–5 0
03066-0-049
Figure 13. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 39 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
AIN = –0.5dBFS
SNR = 70.1dBc
ENOB = 11.3 BITS
SFDR = 81.9dBc
5 10 15 20 25 30
FREQUENCY (MHz)
Figure 11. Single Tone 8K FFT @ 70 MHz
35 40
03066-0-033
100
SFDR (DIFF)
90
SFDR (SE)
80
70
60
SNR (DIFF)
SNR (SE)
50
0
20 40 60 80 100
SAMPLE RATE (MSPS)
03066-0-042
Figure 14. SNR/SFDR vs. Sample Rate @ 10 MHz
Rev. C | Page 11 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9236.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD9230 | 1.8 V Analog-to-Digital Converter | Analog Devices |
| AD9233 | Analog-to-Digital Converter | Analog Devices |
| AD9234 | Dual Analog-to-Digital Converter | Analog Devices |
| AD9235 | 3V A/D Converter | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |