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PDF ISL12021 Data sheet ( Hoja de datos )
| Número de pieza | ISL12021 | |
| Descripción | Real Time Clock | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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 1. Real Time Clock - Intersil  Hay una vista previa y un enlace de descarga de ISL12021 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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ISL12021
®
Real Time Clock with On Chip Temp Compensation ±5ppm
Data Sheet
March 30, 2007
FN6451.0
Low Power RTC with VDD Battery Backed
SRAM and Embedded Temp
Compensation ±5ppm with Auto Day Light
Saving
The ISL12021 device is a low power real time clock with an
embedded Temp sensor for oscillator compensation,
clock/calendar, power fail, low battery monitor, brown out
indicator, single periodic or polled alarms, intelligent battery
backup switching and 128 bytes of battery-backed user
SRAM.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Daylight Savings time adjustment is done automatically,
using parameters entered by the user. Power fail and battery
monitors offer user-selectable trip levels. A time stamp
function records the time and date of switchover from VDD to
battery power, and also from battery to VDD power.
Pinoutwww.DataSheet4U.com
ISL12021
(14 LD TSSOP)
TOP VIEW
NC
X1
X2
VBAT
GND
LVRST
NC
1
2
3
4
5
6
7
14 NC
13 VDD
12 IRQ
11 SCL
10 SDA
9 FOUT
8 NC
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
• On-chip Oscillator Compensation Over the Operating
Temp Range
- ±5ppm over -20°C to +70°C
• Day Light Saving Time
- Customer Programmable
• Separate FOUT pin
- 15 Selectable Frequency Outputs
• 1 Alarm
- Settable to the Second, Minute, Hour, Day of the Week,
Day, or Month
- Single Event or Pulse Interrupt Mode
- Dedicated IRQ output pin
• Automatic Backup to Battery or Super Cap
- Operation to VBAT = 1.8V
- 1.0µA Battery Supply Current
• Battery Status Monitor, 2 Levels, Selectable by Customer
to:
- Seven Selectable Voltages for Each Level
• Power status Brown Out Monitor
- Six selectable trip level, from 4.675V to 2.295V
- Separate Low Voltage LVRST pin
• Time Stamp during Power to Battery and Battery to Power
Cross Over
- Time Stamp. First VDD to VBAT, and Last VBAT to VDD
• 128 Bytes Battery-Backed User SRAM
• I2C Interface
- 400kHz Clock Frequency
• 14 Ld TSSOP package
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Utility Meters
• POS Equipment
• Medical Application
• Security Related Application
• Vending Machine
• White Goods
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL12021
I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -20°C to +70°C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN
(Note 7)
MAX
UNITS NOTES
tR SDA and SCL Rise Time
From 30% to 70% of VDD.
20 + 0.1 x Cb
tF SDA and SCL Fall Time
From 70% to 30% of VDD.
20 + 0.1 x Cb
Cb Capacitive loading of SDA or SCL Total on-chip and off-chip
10
300 ns
300 ns
400 pF
RPU SDA and SCL Bus Pull-up Resistor Maximum is determined by tR
Off-chip
and tF.
For Cb = 400pF, max is about
2~2.5kΩ.
For Cb = 40pF, max is about
15~20kΩ
1
kΩ
NOTES:
2. Temperature Conversion is inactive below 2.7V VBAT
3. IRQ/FOUT Inactive.
4. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz
5. VDD > VBAT +VBATHYS
6. Bit BSW = 0 (Standard Mode), VBAT ≥ 1.8V
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
9. Parameter is not 100% tested.
10. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.
SDA vs SCL Timing
tF
tHIGH
tLOW
tR
SCL
tSU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tSU:DAT
tHD:STA
tHD:DAT
tAA tDH
tSU:STO
tBUF
Symbol Table
WAVEFORM INPUTS
Must be steady
OUTPUTS
Will be steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes Allowed
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not Known
N/A Center Line is
High Impedance
5 FN6451.0
March 30, 2007
5 Page 
ISL12021
TABLE 1. REGISTER MEMORY MAP (Continued)
REG
BIT
ADDR. SECTION NAME
7
6
5
4
3
2
1
0 RANGE DEFAULT
20h DSTCR DstMoFd DSTE
D
D DstMoFd2 DstMoFd1 DstMoFd1 DstMoFd1 DstMoFd1 1 to 12
03210
00h
21h
DstDwFd DstDwEF
D
D
D
D DstDwFd1 DstDwFd1 DstDwFd1 0 to 6
00h
d 210
22h
DstDtFd
D
D DstDtFd2 DstDtFd2 DstDtFd1 DstDtFd1 DstDtFd11 DstDtFd1 1 to 31
00h
1032
0
23h
DstHrFd
D
D DstHrFd2 DstHrFd2 DstHrFd1 DstHrFd1 DstHrFd1 DstHrFd1 0 to 23
00h
103210
24h DstMoRv D D D XDstMoR DstMoRv1 DstMoR12 DstMoRv1 DstMoRv1 01 to 12 00h
v20 3 v 1 0
25h
DstDwRv DstDwER
D
D
D
D DstDwRv1 DstDwRv1 DstDwRv1 0 to 6
00h
v 210
26h
DstDtRv
D
D DstDtRv2 DstDtRv2 DstDtRv1 DstDtRv1 DstDtRv1 DstDtRv1 01 to 31 00h
103210
27h
DstHrRv
D
D DstHrRv2 DstHrRv2 DstHrRv1 DstHrRv1 DstHrRv1 DstHrRv1 0 to 23
00h
103210
28h TEMP TK0L
TK07
TK06
TK05
TK04
TK03
TK02
TK01
TK00 00 to FF
00h
29h
TK0M
0
0
0
0
0
0
TK09
TK08 00 to 03
00h
2Ah GPM GPM1 GPM17 GPM16 GPM15 GPM14 GPM13 GPM12 GPM11 GPM10 00 to FF 00h
2Bh
GPM2 GPM27 GPM26 GPM25 GPM24 GPM23 GPM22 GPM21 GPM20 00 to FF
00h
2Ch
GPM3 GPM37 GPM36 GPM35 GPM34 GPM33 GPM32 GPM31 GPM30 00 to FF
00h
2Dh
GPM4 GPM47 GPM46 GPM45 GPM44 GPM43 GPM42 GPM41 GPM40 00 to FF
00h
2Eh
GPM5 GPM57 GPM56 GPM55 GPM54 GPM53 GPM52 GPM51 GPM50 00 to FF
00h
2Fh
GPM6 GPM67 GPM66 GPM65 GPM64 GPM63 GPM62 GPM61 GPM60 00 to FF
00h
11 FN6451.0
March 30, 2007
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ISL12021.PDF ] | |
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