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PDF X9428 Data sheet ( Hoja de datos )
| Número de pieza | X9428 | |
| Descripción | Single Digitally Controlled Potentiometer | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de X9428 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
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Single Digitally Controlled Potentiometer
(XDCP™)
FEATURES
• Solid state potentiometer
• 2-wire serial interface
• Register oriented format
—Direct Read/Write/Transfer wiper position
—Store as many as four positions per
potentiometer
• Power supplies
—VCC = 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
• Low power CMOS
—Standby current < 1µA
—Ideal for battery operated applications
• High reliability
—Endurance–100,000 Data changes per bit per
register
—Register data retention–100 years
• 4-bytes of nonvolatile memory
• 10kΩ resistor array
•www.DataSheet4U.com Resolution: 64 taps each potentiometer
• 16 Ld SOIC, 14 Ld TSSOP packages
• Pb-free plus anneal available (RoHS compliant)
X9428
Low Noise/Low Power/2-Wire Bus
April 26, 2006
FN8197.1
DESCRIPTION
The X9428 integrates a digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power-up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC
VSS
V+
V–
SCL
SDA
A0
A2
A3
WP
Interface
and
Control
Circuitry
8
Data
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
VH/RH
VL/RL
VW/RW
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
X9428
PRINCIPLES OF OPERATION
The X9428 is a highly integrated microcircuit
incorporating a resistor array and its associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9428 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9428 will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (tLOW). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9428 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (tHIGH). The X9428 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9428 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9428 will respond with a final acknowledge.
Array Description
The X9428 is comprised of a resistor array. The array
contains 63 discrete resistive segments that are
connected in series. The physical ends of the array
are equivalent to the fixed terminals of a mechanical
potentiometer (VH/RH and VL/RL inputs).
At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
(VW/RW) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers and
the WCR can be read and written by the host system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9428
this is fixed as 0101[B].
Figure 1. Slave Address
Device Type
Identifier
0 1 0 1 A3 A2 0 A0
Device Address
The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A0, A2, A3 inputs. The X9428
compares the serial data stream with the address
input state; a successful compare of all four address
bits is required for the X9428 to respond with an
acknowledge. The A0, A2, A3 inputs can be actively
driven by CMOS input signals or tied to VCC or VSS.
5 FN8197.1
April 26, 2006
5 Page 
X9428
Instruction Format
Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
S
T
A
R
T
device type
identifier
0101
device
addresses
A
3
A
2
0
A
0
S
A
C
K
instruction
opcode
1001
0
0
0
0
S
A
C
K
wiper position
(sent by slave on SDA)
MS
AT
0
0
WWWWWW
PPPPPP
543210
C
K
O
P
Write Wiper Counter Register (WCR)
S
T
A
R
T
device type
identifier
0101
device
addresses
A
3
A
2
0
A
0
S
A
C
K
instruction
opcode
1010
0
0
0
0
S
A
C
K
wiper position
(sent by master on SDA)
S
A
0
0
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
C
K
S
T
O
P
Read Data Register (DR)
S
T
A
R
T
device type
identifier
0101
device
addresses
A
3
A
2
0
A
0
S
A
C
K
instruction
opcode
1011
register
addresses
R
1
R
0
0
0
S
A
C
K
wiper position/data
(sent by slave on SDA)
M
A
WWWWWWC
0
0
P
5
P
4
P
3
P
2
P
1
P
0
K
S
T
O
P
Write Data Register (DR)
S
T
A
R
T
device type
identifier
0101
device
addresses
A
3
A
2
0
A
0
S
A
C
K
instruction
opcode
1100
register
addresses
R
1
R
0
0
0
S
A
wiper position/data
(sent by master on SDA)
S
A
S
T
C WWWWWWC O
K
0
0
P
5
P
4
P
3
P
2
P
1
P
0
K
P
HIGH-VOLTAGE
WRITE CYCLE
XFR Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
device type
identifier
0101
device
addresses
A
3
A
2
0
A
0
S
A
C
K
instruction
opcode
1101
register
addresses
R
1
R
0
0
0
S
A
C
K
S
T
O
P
11 FN8197.1
April 26, 2006
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet X9428.PDF ] | |
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