PDF PI2EQX4402 Data sheet ( Hoja de datos )

Número de pieza	PI2EQX4402
Descripción	2.5Gbps x2 Lane Serial PCI Express Repeater/Equalizer
Fabricantes	Pericom Semiconductor
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No Preview Available ! PI2EQX4402 2.5Gbps x2 Lane Serial PCI Express Repeater/Equalizer Features • Two High Speed PCI Express lanes • Supports PCI Express data rates (2.5 Gbps) on each lane • Adjustable Transmiter De-Emphasis & Amplitude • Adjustable Receiver Equalization • Two Spread Spectrum Reference Clock Buffer Outputs • 100Ω Differential CML I/O’s • Low Power (100mW per Channel) • Standby Mode – Power Down State • VDD Operating Range: 1.8V +/-0.1V • Packaging (Pb-free & Green): - 84-ball LFBGA www.DataSheet4U.com Description Pericom Semiconductor’s PI2EQX4402 is a low power, PCI Express compliant signal re-driver. The device provides programmable equalization, amplification, and de-emphasis by using 7 select bits, SEL[0:6], to optimize performance over a variety of physical mediums by reducing Inter-symbol interference. PI2EQX4402 supports four 100 Differential CML data I/O’s between the Protocol ASIC to a switch fabric, across a backplane, or extends the signals across other distant data pathways on the user’s platform. The integrated equalization circuitry provides flexibility with signal integrity of the PCI Express signal before the re-driver. Whereas the integrated de-emphasis circuitry provides flexibility with signal integrity of the PCI Express signal after the re-driver. In addition to providing signal re-conditioning, Pericom’s PI2EQX4402 also provides power management Stand-by mode operated by a Bus Enable pin. Block Diagram �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� �� Pin Description (Top View) � � � � � � � � � �� � �� �� � �� � �� �� � �� �� � �� � �� � �� �� �� �� �� �� � �� �� � �� � �� 1 PS8778E 02/15/06 1 page PI2EQX4402 2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer AC/DC Electrical Characteristics for 2.5 Gbps x2 Lane Repeater/Equalizer (TA = 0 to 70˚C) Symbol Parameter Conditions Min. Typ. Max. Units CML Transmitter Output (100Ω differential) VDIFFP Output Voltage Swing Differential Swing \| VTX-D+ - VTX-D- \| VTX-C tF, tR ZOUT ZTX-DIFF-DC CTX VTX-DIFFP-P Common-Mode Voltage Transition Time Output resistance DC Differential TX Impedance AC Coupling Capacitor Differential Peak-to-peak Ouput Voltage \| VTX-D+ + VTX-D- \| / 2 20% to 80% (1) Single ended VTX-DIFFP-P = 2 * \| VTX-D+ - VTX-D- \| 400 40 80 75 0.8 VDD- 0.3 50 100 900 mVp-p 150 ps 60 Ω 120 Ω 200 nF 1.8 V LVCMOS Control Pins VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current 0.65 × VDD VDD 0.35 × VDD 250 500 V µA Note: 1. Using K28.7 (0011111000) pattern) 5 PS8778E 02/15/06 5 Page

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