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PDF AT24HC02B Data sheet ( Hoja de datos )
| Número de pieza | AT24HC02B | |
| Descripción | Two-wire Serial EEPROM | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Write Protect Pin for Hardware Data Protection
– Utilizes Different Array Protection Compared to the AT24C02B
• Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8V to 5.5V)
• Internally Organized 256 x 8 (2K)
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (5V) and 400 kHz (1.8V, 2.5V, 2.7V) Clock Rate
• 8-byte Page
• Partial Page Writes Allowed
• Self-timed Write Cycle (5 ms Max)
• High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
• 8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP Packages
• Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
Description
The AT24HC02B provides 2048 bits of serial electrically erasable and programmable
read-only memory (EEPROM) organized as 256 words of 8 bits each. The device is opti-
mized for use in many industrial and commercial applications where low-power and low-
voltage operation are essential. The AT24HC02B is available in space-saving 8-lead
PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP packages and is accessed via a two-wire
serial interface. In addition, the entire family is available in 1.8V (1.8V to 5.5V) version.
Two-wire Serial
EEPROM
2K (256 x 8)
AT24HC02B
Preliminary
Table 1.www.DataSheet4U.com Pin Configuration
Pin Name
Function
A0–A2
Address Inputs
SDA
Serial Data
SCL Serial Clock Input
WP Write Protect
8-lead TSSOP
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
8-lead PDIP
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
8-lead SOIC
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
Rev. 5134C–SEEPR–3/07
1
1 page  
AT24HC02B [Preliminary]
Table 5. AC Characteristics
Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
1.8, 2.5, 2.7
5.0-volt
Symbol
Parameter
Min Max Min Max
Units
fSCL
tLOW
tHIGH
tI
tAA
tBUF
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
Clock Low to Data Out Valid
Time the bus must be free before a new
transmission can start
400 1000
1.2 0.4
0.6 0.4
50 40
0.1 0.9 0.05 0.55
1.2 0.5
kHz
µs
µs
ns
µs
µs
tHD.STA
Start Hold Time
tSU.STA
Start Setup Time
tHD.DAT
Data In Hold Time
tSU.DAT
Data In Setup Time
tR Inputs Rise Time(1)
tF Inputs Fall Time(1)
tSU.STO
Stop Setup Time
tDH Data Out Hold Time
tWR
Endurance(1)
Write Cycle Time
5.0V, 25°C, Byte Mode
Note: 1. This parameter is ensured by characterization only.
0.6 0.25
0.6 0.25
00
100 100
0.3 0.3
300 100
0.6 .25
50 50
55
1M
µs
µs
µs
ns
µs
ns
µs
ns
ms
Write Cycles
5134C–SEEPR–3/07
5
5 Page 
AT24HC02B [Preliminary]
Figure 12. Sequential Read
tial read will continue. The sequential read operation is terminated when the
microcontroller does not respond with a “0” but does generate a following stop condition,
see Figure 12.
5134C–SEEPR–3/07
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AT24HC02B.PDF ] | |
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