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PDF AT25FS040 Data sheet ( Hoja de datos )
| Número de pieza | AT25FS040 | |
| Descripción | High Speed Small Sectored SPI Flash Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
– Datasheet describes Mode 0 Operation
• 50 MHz Clock Rate
• Byte Mode and Page Mode Program (1 to 256 Bytes) Operations
• Sector/Block/Page Architecture
– Sixteen 256 byte Pages per Sector
– Sixteen 4 Kbyte Sectors per Block
– Eight uniform 64 Kbyte Blocks
• Self-timed Sector, Block and Chip Erase
• Product Identification Mode with JEDEC Standard
• Low-voltage Operation
– 2.7V (VCC = 2.7V to 3.6V)
• Hardware and Software Write Protection
– Device protection with Write Protect (WP) Pin
– Write Enable and Write Disable Instructions
– Software Write Protection:
Upper 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 or Entire Array
• Flexible Op Codes for Maximum Compatibility
• Self-timed Program Cycle
– 30 µs/Byte Typical
• Single Cycle Reprogramming (Erase and Program) for Status Register
• High Reliability
– Endurance: 10,000 Write Cycles Typical
• 8-lead JEDEC 150mil SOIC and 8-lead Ultra Thin Small Array Package (SAP)
High Speed
Small Sectored
SPI Flash
Memory
4M (524,288 x 8)
AT25FS040
Description
www.DataSheet4U.com
The AT25FS040 provides 4,194,304 bits of serial reprogrammable Flash memory
organized as 524,288 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT25FS040 is available in a space-saving 8-lead JEDEC SOIC and
8-lead Ultra Thin SAP packages.
Table 1. Pin Configuration
Pin Name
Function
CS Chip Select
SCK
Serial Data Clock
SI Serial Data Input
SO Serial Data Output
GND
Ground
VCC
Power Supply
WP Write Protect
HOLD
Suspends Serial
Input
8-lead JEDEC SOIC
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
8-lead SAP
__V_C_C_ 8
HOLD 7
SCK 6
___
1 CS
2 _S_O_
3 WP
SI 5
4 GND
Bottom View
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Information
5107D–SFLSH–09/06
1 page  
AT25FS040
Serial Interface
Description
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25FS040 always
operates as a slave.
TRANSMITTER/RECEIVER: The AT25FS040 has separate pins designated for data
transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25FS040, and the serial output pin (SO) will remain in a high impedance state until
the falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25FS040 is selected when the CS pin is low. When the device is
not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will
remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25FS040.
When the device is selected and a serial sequence is underway, HOLD can be used to
pause the serial communication with the master device without resetting the serial
sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought high while the SCK pin is low
(SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin
is in the high impedance state.
WRITE PROTECT: The AT25FS040 has a write lockout feature that can be activated by
asserting the write protect pin (WP). When the lockout feature is activated, locked-out
sectors will be READ only. The write protect pin will allow normal read/write operations
when held high. When the WP is brought low and WPEN bit is “1”, all write operations to
the status register are inhibited. WP going low while CS is still low will interrupt a write to
the status register. If the internal status register write cycle has already been initiated,
WP going low will have no effect on any write operation to the status register. The WP
pin function is blocked when the WPEN bit in the status register is “0”. This will allow the
user to install the AT25FS040 in a system with the WP pin tied to ground and still be
able to write to the status register. All WP pin functions are enabled when the WPEN bit
is set to “1”.
Operating Features
Recommended Power-up
When the power supply is turned on, the Vcc to the device rises monotonically from
ground to the full operating Vcc. During this time, the Chip Select (CS) signal is not
allowed to float and must follow Vcc. For this reason, it is recommended to use a suit-
able pull-up resistor connected between CS and Vcc. The device is ready for
communication once a stable Vcc is reached within the specified operating voltage
range.
Recommended Power-
down
The device must be deselected and in standby and write disabled mode prior to Vcc
power down sequence. This means there should be no write operation/internal write
cycle or read operation in progress during power down. The Vcc decay should be mono-
tonic from Vcc to ground and the Chip Select (CS) line must be allowed to follow Vcc
during power down. After power down, it is recommended Vcc should be held at ground
level for at least 0.5 seconds before power up again.
5107D–SFLSH–09/06
5
5 Page 
AT25FS040
progress. If Bit 0=0, the programming cycle has ended. Only the RDSR instruction is
enabled during the programming cycle and all other opcode instructions are ignored
until programming cycle has completed.
A single PROGRAM instruction programs 1 to 256 consecutive bytes within a page if it
is not write protected. The starting byte address can be anywhere within the page.
When the end of the page is reached, the address will wrap around to the beginning of
the same page. If the data to be programmed is less than a full page, the data of all
other bytes on the same page will remain unchanged meaning that the unwritten
address locations within the page will not be changed. If more than 256 bytes of data
are provided, the address counter will roll over on the same page and the previous data
provided will be replaced. The same byte cannot be reprogrammed without erasing the
whole sector or block first. The AT25FS040 will automatically return to the write disable
state at the completion of the programming cycle.
Note:
If the device is not write enabled (WREN), the device will ignore the Write instruction and
will return to the standby state when CS is brought high. A new CS falling edge is
required to re-initiate the serial communication.
Table 11. Address Key
Address
AN
Don’t Care Bits
AT25FS040
A18 - A0
A23 - A19
ERASE OPERATION: The AT25FS040 memory array is internally organized into uni-
form 4K byte sectors or uniform 64K byte uniform blocks (see Table 12). Before data can
be reprogrammed, the sector or block that contains the data must be erased first. In
order to erase the AT25FS040, there are three flexible erase instructions that can be
executed as follows: SECTOR ERASE, BLOCK ERASE and CHIP ERASE instructions.
A SECTOR ERASE instruction allows erasing any individual 4K sector without changing
data in rest of memory. The BLOCK ERASE instruction allows erasing any individual
block and CHIP ERASE allows erasing the entire memory array.
SECTOR ERASE (SECTOR ERASE): The SECTOR ERASE instruction sets all 4K
bytes in the selected sector to logic 1 or erased state. In order to sector erase the
AT25FS040, two separate instructions must be executed. First, the device must be write
enabled via the WREN instruction. Then the SECTOR ERASE instruction can be exe-
cuted and will erase every byte in the selected sector if the sector is not locked out. The
sector address is automatically determined if any address within the sector is selected
(see Figure 12). The SECTOR ERASE instruction is internally controlled and self timed
to completion. During this time, all commands will be ignored except RDSR instruction.
The progress or completion of the erase operation can be determined by reading
ready/busy bit (bit 0) through RDSR instruction. If Bit 0=1, sector erase cycle is in
progress. If Bit 0=0, the erase operation has been completed. The AT25FS040 will auto-
5107D–SFLSH–09/06
11
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| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet AT25FS040.PDF ] | |
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