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PDF AT83C26 Data sheet ( Hoja de datos )
| Número de pieza | AT83C26 | |
| Descripción | Multiple Smart Card Reader Interface | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• 5 Smart Card Interfaces
– Compliance with ISO 7816, EMV2000, GIE-CB and GSM Standards
– Direct Connection to the Smart Cards
Logic Level Shifters
Short Circuit Current Limitation
4kV+ ESD Protection (MIL/STD 883 Class 3)
– 1 or 2 Master Smart Card interfaces
Synchronous Card support (with C4 and C8 Contacts)
Card Detection and Automatic de-activation sequence on card extraction
– 1 to 4 SAM/SIM cards (15 to 30mA each)
– Programmable Voltage for each smart card
Class A: 5V ±0.4V at 60 mA (±0.25V at 65 mA with VCC= 5V±10%)
Class B: 3V ±0.2V at 60 mA
Class C: 1.8V ±0.14V at 40mA
– Low Ripple Noise: < 200 mV
– Programmable Activation Sequence
– Automatic de-activation on card power-fail or over-current and system power-fail
– Card Clock Stop High or Low for Card Power-down Modes
• Versatile Host Interface
– Two Wire Interface (TWI) Link at 400kbit/s
Programmable Address allow up to 4 AT83C26 on the bus
– Programmable Interrupt Output
• Reset Output Includes
– Power-On Reset (POR)
– Power-Fail Detector (PFD)
• Extended Voltage Operation: 3 to 5.5V
• Low Power Consumption
– 5 mA Maximum Operating Current (without Smart Card)
–www.DataSheet4U.com 150 mA Maximum In-rush Current (each DC/DC)
– 30 µA Typical Power-down Current (without Smart Card)
• 4 to 48 MHz Clock Input
• System clock derived from the external clock input
• Industrial Temperature Range: -40 to +85°C
• Packages: QFN48, VQFP48
Multiple Smart
Card Reader
Interface With
Power
Management
AT83C26
Description
The AT83C26 is a smart card reader interface IC for smart card reader/writer applica-
tions such as EFT/POS terminals and set top boxes. It enables the management of
any type of smart card from any kind of host. Up to 4 AT83C26 can be connected in
parallel thanks to the programmable TWI address.
Its high efficiency DC/DC converters and low quiescent current in stand-by mode
make it particularly suited to low power and portable applications. The reduced bill of
material allows to lower significantly the system size and cost. A sophisticated protec-
tion system guarantees timely and controlled shutdown upon error conditions.
7511D–SCR–02/07
1 page  
AT83C26
Table 1. Ports Description (Continued)
VQFP48 or
QFN48
Pin number
Pad Name
Pad Internal
Power Supply
Pad Type
Description
22 LIA
PWR
DC/DCA input.
LIA must be tied to VCC pin through an external coil (typically 10µH) and
provides the current for the charge pump of the DC/DCA converter.
It may be directly connected to VCC if the step-up converter is not used
(see STEPREGA bit in SC1_CFG4 register and see minimum VCC
values in Table 50.for class A and Table 51. for class B)
23 CVSS1
GND
DC/DCA input.
This pin must be directly connected to the VSS of power supply.
24 VCC
PWR VCC is used to power the internal voltage regulators and I/O buffers.
25 VSS
GND Ground.
26 BYPASS
VCC
I
A high level on this pin activates a low power consumption mode with
internal regulator bypassed.
27 SDA
VCC
I/O Micro controller interface function: TWI serial data.
open drain An external pull up must be connected on SDA pin (4.7kOhms).
28 SCL
VCC
I/O Micro controller interface function: TWI clock.
open drain An external pull up must be connected on SCL pin (4.7kOhms).
29 IO2
EVCC
I/O The behavior of this pin depends on IOSEL[3/0] bits values (see
pull up IO_SELECT register).
30 IO1
EVCC
I/O The behavior of this pin depends on IOSEL[3/0] bits values (see
pull up IO_SELECT register).
31 AUX2
EVCC
I/O The behavior of this pin depends on IOSEL[3/0] bits values (see
pull up IO_SELECT register).
32 AUX1
EVCC
I/O The behavior of this pin depends on IOSEL[3/0] bits values (see
pull up IO_SELECT register).
33 A1/RST
EVCC
The TWI address depends on the value present on this pin at reset.
I If CRST transparent mode is selected, the A1/RST signal is connected to
CRST1 or CRST2 pins (see CRST_SEL1 and CRST_SEL2 bits
respectively in SC1_CFG4 and SC2_CFG2 registers).
34 A2/CK
EVCC
The TWI address depends on the value present on this pin at reset.
If CCLKn transparent mode is selected, the A2/CK signal is connected to
I CCLKn pins (with n=1 to 5).
See CKSn[2:0] bits respectively in SC1_CFG1, SC2_CFG2, SC3_CFG2,
SC4_CFG2, SC5_CFG2 registers.
35 CLK
EVCC
I Master clock.
36 INT
37 EVCC
VCC
O Interruption status.
open drain
An internal pull up to VCC can be activated in the pin if necessary using
INT_PULLUP bit in SC1_CFG4 (deactivated by default).
PWR
Extra supply voltage (Micro controller power supply).
EVCC is used to supply the internal level shifters of host interface pins.
EVCC is connected to the host power supply.
EVCC voltage can be directly connected to VCC if the host power supply
and the AT83C26 power supply is the same.
7511D–SCR–02/07
5
5 Page 
Figure 1. Data transfer on TWI bus
SDA
Address byte
AT83C26
acknowledgement
from slave
command
and/or data
SCL
12 3 45 678 9
start condition
stop condition
Address Byte
7511D–SCR–02/07
The first byte to send to the device is the address byte. The device controls if the hardware
address (A2/CK, A1/RST pins on reset) corresponds to the address given in the address byte
(A2, A1 bits).
If the level is not stable on A2/CK pin at reset, the user has to manage the possible address
taken by the device.
Figure 2. Address Byte
b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 0 A2 A1 1 R/W
Slave Address on 7 Bits
1 for READ Command
0 for WRITE Command
Up to 4 devices can be connected on the same TWI bus. Each device is configured with a differ-
ent combination on A2/CK, A1/RST pins. The address byte of each device for read/write
operations are listed below.
Table 2. Address Byte Values
A2
(A2/CK pin)
A1
(A1/RST pin)
00
01
10
11
Address Byte
for
Read
Command
0x43
0x47
0x4B
0x4F
Address Byte
for
Write
Command
0x42
0x46
0x4A
0x4E
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT83C26.PDF ] | |
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