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PDF AT93C46D Data sheet ( Hoja de datos )
| Número de pieza | AT93C46D | |
| Descripción | 3-wire Serial EEPROM | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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AT93C46D
3-wire Serial EEPROM
1K (128 x 8 or 64 x 16)
DATASHEET
Features
Low-voltage Operation
̶ VCC = 1.8V to 5.5V
User-selectable Internal Organization
̶ 1K: 128 x 8 or 64 x 16
3-wire Serial Interface
2MHz Clock Rate (5V)
Self-timed Write Cycle (5ms Max)
High Reliability
̶ Endurance: 1,000,000 Write Cycles
̶ Data Retention: 100 Years
8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-lead PDIP, and
8-ball VFBGA Packages
Description
The Atmel® AT93C46D provides 1,024 bits of Serial Electrically Erasable
Programmable Read-Only Memory (EEPROM) organized as 64 words of 16 bits
each (when the ORG pin is connected to VCC) and 128 words of 8 bits each (when
the ORG pin is tied to ground). The device is optimized for use in many industrial
and commercial applications where low-power and low-voltage operations are
essential. The AT93C46D is available in space-saving 8-lead JEDEC SOIC,
8-lead TSSOP, 8-pad UDFN, 8-lead PDIP, and 8-ball VFBGA packages.
The AT93C46D is enabled through the Chip Select pin (CS) and accessed via a
3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a Read instruction at DI, the address is decoded, and
the data is clocked out serially on the DO pin. The write cycle is completely
self-timed, and no separate erase cycle is required before Write. The write cycle is
only enabled when the part is in the Erase/Write Enable state. When CS is
brought high following the initiation of a write cycle, the DO pin outputs the
Ready/Busy status of the part.
The AT93C46D operates from 1.8V to 5.5V.
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
1 page  
4.3 AC Characteristics
Table 4-3. AC Characteristics
Applicable over recommended operating range from TAI = 40°C to + 85°C, VCC = as specified,
CL = 1 TTL gate and 100pF (unless otherwise noted).
Symbol
fSK
tSKH
tSKL
tCS
tCSS
tDIS
tCSH
tDIH
tPD1
tPD0
tSV
tDF
tWP
Endurance(1)
Parameter
SK Clock Frequency
SK High Time
SK Low Time
Minimum CS Low Time
CS Setup Time
DI Setup Time
CS Hold Time
DI Hold Time
Output Delay to 1
Output Delay to 0
CS to Status Valid
CS to DO in
High-impedance
Write Cycle Time
5.0V, 25°C
Test Condition
4.5V VCC 5.5V
2.7V VCC 5.5V
1.8V VCC 5.5V
4.5V VCC 5.5V
2.7V VCC 5.5V
1.8V VCC 5.5V
4.5V VCC 5.5V
2.7V VCC 5.5V
1.8V VCC 5.5V
4.5V VCC 5.5V
2.7V VCC 5.5V
1.8V VCC 5.5V
4.5V VCC 5.5V
Relative to SK 2.7V VCC 5.5V
1.8V VCC 5.5V
4.5V VCC 5.5V
Relative to SK 2.7V VCC 5.5V
1.8V VCC 5.5V
Relative to SK
Relative to SK
AC Test
AC Test
AC Test
AC Test
CS = VIL
4.5V VCC 5.5V
2.7V VCC 5.5V
1.8V VCC 5.5V
4.5V VCC 5.5V
2.7V VCC 5.5V
1.8V VCC 5.5V
4.5V VCC 5.5V
2.7V VCC 5.5V
1.8V VCC 5.5V
4.5V VCC 5.5V
2.7V VCC 5.5V
1.8V VCC 5.5V
4.5V VCC 5.5V
2.7V VCC 5.5V
1.8V VCC 5.5V
1.8V VCC 5.5V
Min Typ Max
02
01
0 250
250
250
1000
250
250
1000
250
250
1000
50
50
200
100
100
400
0
100
400
250
250
1000
250
250
1000
250
250
1000
100
250
400
0.1 3
5
1,000,000
Units
MHz
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Write Cycles
Note: 1. This parameter is characterized, and is not 100% tested.
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
5
5 Page 
Figure 6-7. ERASE Timing
CS
SK
DI
111
AN AN-1 AN-2 ... A0
DO High-impedance
tCS
Check
Status
Standby
tSV
Busy
Ready
tDF
High-impedance
tWP
Figure 6-8. ERAL Timing(1)
CS
SK
tCS
Check
Status
Standby
DI 1 0 0 1 0
DO High-impedance
tSV
Busy
Ready
tDF
High-impedance
Note:
tWP
1. Valid only at VCC3 (Section 4.2, “DC Characteristics” on page 4).
AT93C46D [DATASHEET]
Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015
11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet AT93C46D.PDF ] | |
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