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PDF AT93C46E Data sheet ( Hoja de datos )
| Número de pieza | AT93C46E | |
| Descripción | Three-wire Serial EEPROM | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8V to 5.5V)
• Internal Organization
– 64 x 16
• Three-wire Serial Interface
• 2 MHz Clock Rate (5V) Compatibility
• Self-timed Write Cycle (5 ms max)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• 8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP Packages
• Lead-free/Halogen-free Devices
Description
The AT93C46E provides 1024 bits of serial electrically-erasable programmable read-
only memory (EEPROM) organized as 64 words of 16 bits each. The device is opti-
mized for use in many industrial and commercial applications where low-power and
low-voltage operation are essential. The AT93C46E is available in space-saving 8-
lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP packages.
The AT93C46E is enabled through the Chip Select pin (CS) and accessed via a three-
wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock
(SK). Upon receiving a Read instruction at DI, the address is decoded and the data is
clocked out serially on the data output DO pin. The write cycle is completely self-timed
and no separate erase cycle is required before write. The write cycle is only enabled
when the part is in the erase/write enable state. When CS is brought high following the
www.DataSheeti4nU.ictoimation of a write cycle, the DO pin outputs the ready/busy status of the part.
The AT93C46E is available in 1.8V (1.8V to 5.5V) version.
Table 1. Pin Configuration
Pin Name
Function
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
GND
Ground
VCC
Power Supply
NC No Connect
8-lead PDIP
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 NC
5 GND
8-lead SOIC
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 NC
5 GND
8-lead TSSOP
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 NC
5 GND
Three-wire
Serial EEPROM
1K (64 x 16)
AT93C46E
Preliminary
Rev. 5207A–SEEPR–1/07
1
1 page  
AT93C46E [Preliminary]
Functional
Description
The AT93C46E is accessed via a simple and versatile three-wire serial communication
interface. Device operation is controlled by seven instructions issued by the host pro-
cessor. A valid instruction starts with a rising edge of CS and consists of a start bit (logic
“1”) followed by the appropriate op code and the desired memory address location.
Table 5. Instruction Set for the AT93C46E
Address
Instruction SB Op Code
x 16
READ
EWEN
1
1
10
00
A5 − A0
11XXXX
ERASE
WRITE
ERAL
1
1
1
11
01
00
A5 − A0
A5 − A0
10XXXX
WRAL
1
00
01XXXX
EWDS
1
00
00XXXX
Comments
Reads data stored in memory, at specified address
Write enable must precede all programming modes
Erase memory location An − A0
Writes memory location An − A0
Erases all memory locations. Valid only at VCC = 4.5V to 5.5V
Writes all memory locations. Valid only at VCC = 4.5V to 5.5V
Disables all programming instructions
READ (READ): The Read (READ) instruction contains the address code for the mem-
ory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 16-bit data output string.
ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes
into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write
Enable (EWEN) instruction must be executed first before any programming instructions
can be carried out. Please note that once in the EWEN state, programming remains
enabled until an EWDS instruction is executed or VCC power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
Erase instruction and address are decoded. The DO pin outputs the ready/busy status
of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A
logic “1” at pin DO indicates that the selected memory location has been erased and the
part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 16 bits of data to be writ-
ten into the specified memory location. The self-timed programming cycle, tWP, starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
ready/busy status of the part if CS is brought high after being kept low for a minimum of
250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic “1”
indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A
ready/busy status cannot be obtained if the CS is brought high after the end of the self-
timed programming cycle, tWP.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-
ory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the ready/busy status of the part if CS is brought high after being kept low for a
minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the ready/busy
5207A–SEEPR–1/07
5
5 Page 
Packaging Information
8P3 – PDIP
1
AT93C46E [Preliminary]
E
E1
N
Top View
c
eA
End View
D
e
D1 A2 A
b3
4 PLCS
b2
b
Side View
L
COMMON DIMENSIONS
(Unit of Measure = inches)
SYMBOL
A
A2
b
b2
b3
c
D
D1
E
E1
e
eA
L
MIN NOM MAX
0.210
0.115 0.130 0.195
0.014 0.018 0.022
0.045 0.060 0.070
0.030 0.039 0.045
0.008 0.010 0.014
0.355 0.365 0.400
0.005
0.300 0.310 0.325
0.240 0.250 0.280
0.100 BSC
0.300 BSC
0.115 0.130 0.150
NOTE
2
5
6
6
3
3
4
3
4
2
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
2325 Orchard Parkway
R San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO. REV.
8P3 B
5207A–SEEPR–1/07
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet AT93C46E.PDF ] | |
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