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PDF ATA3742 Data sheet ( Hoja de datos )
| Número de pieza | ATA3742 | |
| Descripción | UHF ASK/FSK Receiver | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• IC Distinguishes the Signal Strength of Several Transmitters via RSSI (Received Signal
Strength Indicator) Output
• Minimal External Circuitry Requirements, No RF Components on the PC Board Except
Matching to the Receiver Antenna
• High Sensitivity, Especially at Low Data Rates
• Sensitivity Reduction Possible Even While Receiving
• Fully Integrated VCO
• Low Power Consumption Due to Configurable Self-polling With a
Programmable Time Frame Check
• Supply Voltage 4.5V to 5.5V
• Operating Temperature Range –40°C to +105°C
• Single-ended RF Input for Easy Adaptation to λ / 4 Antenna or Printed
Antenna on PCB
• Low-cost Solution Due to High Integration Level
• ESD Protection According to MIL-STD. 883 (4 KV HBM)
• High Image Frequency Suppression Due to 1 MHz IF in Conjunction With a SAW
Front-end Filter (Up to 40 dB Achievable With Newer SAWs)
• Communication to Microcontroller Possible via a Single, Bi-directional Data Line
• Power Management (Polling) is also Possible by Means of a Separate Pin via the
Microcontroller
UHF ASK/FSK
Receiver
ATA3742
www.DataSheet4U.com
1. Description
The ATA3742 is a multi-chip PLL receiver device supplied in an SO20 package. It has
been specially developed for the demands of RF low-cost data transmission systems
with data rates from 1 kBaud to 10 kBaud (1 kBaud to 3.2 kBaud for FSK) in
Manchester or Bi-phase code. The receiver is well-suited to operate with Atmel’s PLL
RF transmitter IC U2741B. Its main applications in the area of wireless control are
telemetering, security technology, tire-pressure monitoring and keyless-entry sys-
tems. It can be used in the frequency receiving range of f0 = 300 MHz to 450 MHz for
ASK or FSK data transmission. All the statements made in this datasheet refer both to
433.92 MHz and 315 MHz applications.
Rev. 4900A–RKE–11/05
1 page  
ATA3742
To determine fLO, the construction of the IF filter must be considered at this point. The nominal IF
frequency is fIF = 1 MHz. To achieve a good accuracy of the filter's corner frequencies, the filter
is tuned by the crystal frequency fXTO. This means that there is a fixed relation between fIF and
fLO that depends on the logic level at pin MODE. This is described by the following formulas:
MODE
=
0
(USA) fIF
=
-f--L---O---
314
MODE
=
1 (Europe) fIF
=
------f--L--O-------
432.92
The relation is designed to achieve the nominal IF frequency of fIF = 1 MHz for most applica-
tions. For applications where fRF = 315 MHz, MODE must be set to “0”. In the case of
fRF = 433.92 MHz, MODE must be set to “1”. For other RF frequencies, fIF is not equal to 1 MHz.
fIF is then dependent on the logical level at pin MODE and on fRF. Table 3-1 summarizes the dif-
ferent conditions.
The RF input either from an antenna or from a generator must be transformed to the RF input
pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The para-
sitic board inductances and capacitances also influence the input matching. The RF receiver
ATA3742 exhibits its highest sensitivity at the best signal-to-noise ratio in the LNA. Hence, noise
matching is the best choice for designing the transformation network.
A good practice when designing the network is to start with power matching. From that starting
point, the values of the components can be varied to some extent to achieve the best sensitivity.
If a SAW is implemented into the input network, a mirror frequency suppression of ∆PRef = 40 dB
can be achieved. There are SAWs available that exhibit a notch at ∆f = 2 MHz. These SAWs
work best for an intermediate frequency of IF = 1 MHz. The selectivity of the receiver is also
improved by using a SAW. In typical automotive applications, a SAW is used.
Figure 3-2 on page 6 shows a typical input matching network for fRF = 315 MHz and
fRF = 433.92 MHz using a SAW. Figure 3-3 on page 6 illustrates input matching to 50Ω without a
SAW. The input matching networks shown in Figure 3-3 on page 6 are the reference networks
for the parameters given in the “Electrical Characteristics” on page 26.
Table 3-1. Calculation of LO and IF Frequency
Conditions
fRF = 315 MHz, MODE = 0
fRF = 433.92 MHz, MODE = 1
Local Oscillator Frequency
fLO = 314 MHz
fLO = 432.92 MHz
Intermediate Frequency
fIF = 1 MHz
fIF = 1 MHz
300 MHz < fRF < 365 MHz, MODE = 0
fLO
=
------f--R----F-------
1 + ----1-----
314
fIF
=
-f--L---O---
314
365 MHz < fRF < 450 MHz, MODE = 1
fLO
=
-----------f-R----F-----------
1 + --------1---------
432.92
fIF
=
------f--L--O-------
432.92
4900A–RKE–11/05
5
5 Page 
ATA3742
5. Polling Circuit and Control Logic
The receiver is designed to consume less than 1 mA while being sensitive to signals from a cor-
responding transmitter. This is achieved via the polling circuit. This circuit enables the signal
path periodically for a short time. During this time, the bit check logic verifies the presence of a
valid transmitter signal. Only if a valid signal is detected does the receiver remain active and
transfer the data to the connected microcontroller. If there is no valid signal present, the receiver
is in sleep mode most of the time, resulting in low current consumption. This condition is called
polling mode. A connected microcontroller is disabled during that time.
All relevant parameters of the polling logic can be configured by the connected microcontroller.
This flexibility enables the user to meet the specifications in terms of current consumption, sys-
tem response time, data rate, etc.
Regarding the number of connection wires to the microcontroller, the receiver is very flexible. It
can be either operated by a single bi-directional line to save ports to the connected microcontrol-
ler, or it can be operated by up to three uni-directional ports.
5.1 Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry and the analog filtering is derived from one clock.
According to Figure 5-1 on page 11, this clock cycle TClk is derived from the crystal oscillator
(XTO) in combination with a divider. The division factor is controlled by the logical state at pin
MODE. As described in Section “RF Front End” on page 4, the frequency of the crystal oscillator
(fXTO) is defined by the RF input signal (fRFin), which also defines the operating frequency of the
local oscillator (fLO).
Figure 5-1. Generation of the Basic Clock Cycle
TCLK
Divider
:14/:10
fXTO
XTO
MODE
16
L : USA(:10)
H: Europe(:14)
DVCC
15
XTO
14
Pin MODE can now be set in accordance with the desired clock cycle TClk. TClk controls the fol-
lowing application-relevant parameters:
• Timing of the polling circuit including bit check
• Timing of the analog and digital signal processing
• Timing of the register programming
• Frequency of the reset marker
• IF filter center frequency (fIF0)
4900A–RKE–11/05
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ATA3742.PDF ] | |
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