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PDF ATA5278 Data sheet ( Hoja de datos )
| Número de pieza | ATA5278 | |
| Descripción | STAND-ALONE ANTENNA DRIVER | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• SPI for Microcontroller Connection with Up to 1 Mbit/s
• Internal Data Buffer for Timing-independent Data Transmission
• Programmable Driver Current Regulation
• One-chip Antenna Driver Stage for 1A Peak Current
• LF Baud Rates Between 1 kbaud and 4 kbaud
• Quick Start Control (QSC) for Fast Oscillation Build-up and Decay Timing
• Integrated Oscillator for Ceramic Resonators
• Power Supply Range from 7.5V to 16V Direct Battery Input
(Up to 28V With Limited Function Range)
• Amplitude Shift Keying (ASK) Modulation
• Phase Shift Keying (PSK) Modulation
• Carrier Frequency Range from 100 kHz to 150 kHz
• Operational Temperature –40°C to +105°C
• EMI and ESD According to Automotive Requirements
• Highly Integrated — Less External Components Required
Applications
• Hands-free Car Access (Passive Entry/Go)
• Tire Pressure Measurement
• Home Access Control
• Care Watch Systems
Benefitswww.DataSheet4U.com
• Diagnosis Function and Overtemperature Protection
• Load Dump Protection Up to 45V for 12V Boards
• Power-down Mode for Minimum Power Consumption
Stand-alone
Antenna Driver
ATA5278
1. Description
The ATA5278 device is an integrated BCDMOS antenna driver IC dedicated as a
transmitter for Passive Entry/Go (PEG) car applications and for other hands-free
access control applications.
It includes the full functionality of generating a magnetic LF field in conjunction with an
antenna coil to transmit data to a receiver in a key fob, card or transponder. A micro-
controller can access the chip via a bi-directional serial interface.
Rev. 4832C–RKE–02/06
1 page  
4832C–RKE–02/06
Figure 3-1. Power-up Timing
ATA5278
S_CS
OSCI/OSCO
QSC
DRV1
Oscillation build-up
Steady oscillation
Z
tstartup
Legend: Z = high impedance
tdeb
The startup time, tstartup, in Figure 3-1 depends on the clock source used in the application. Typi-
cal oscillation build-up times are below 100 µs for ceramic and about 1 ms for crystal resonators.
When using an active clock source, the startup time can be neglected. The internal logic
debounces the first clock signals until it finally powers-up the IC for the time tdeb. Note that during
this time, the chip select signal S_CS has to be permanently active.
The normal way to bring the chip back into power-down mode is to use an SPI command. Deac-
tivating the chip-select line right after the power-down command, an internal standby timer is
started and will run for ttimeout = (2048/fOSCI). In this time, the antenna driver stage is stopped to
discharge any energies possibly remaining in the antenna circuit. If the chip-select line is reacti-
vated during this time, the sequence is interrupted and the IC remains in standby mode.
Otherwise, the power-down mode is engaged after the timeout, the oscillator is stopped and the
driver stages are switched to high impedance. Figure 3-2 illustrates this behavior.
Figure 3-2. Power-down Timing
S_CS
S_CLK
S_DI
DRV1
OSC
8 CLK
cmd 4
X
f = 8 MHz
ttimeout
Legend: X = do not care
Z = high impedance
Z
Note that if command 4 is omitted and only the chip-select line is disabled, the ATA5278 stays
operational (i.e., the oscillator keeps running, an eventually running LF data modulation is not
interrupted). Here, only the SPI itself is disabled and the serial bus can be used for other devices
connected to it.
5
5 Page 
ATA5278
3.8 Command Description
Table 3-1 on page 10 summarizes the commands interpreted by the SPI control logic of the
ATA5278. Each command consists of one or more data words which the controller has to trans-
fer to the SPI of the ATA5278. An SPI data word is always eight bits in width and has to be
transferred starting with the least significant bit (LSB).
The following list contains detailed information on every command of the chip.
• The main purpose of command 1 is to check the operational status of the chip. Only if the
System-Ready bit (SR) and the Ready-To-Send bit (RTS) have been received as 1, the
ATA5278 is fully functional. In special cases, only the SR bit will be received as 1. This is
when the LF data buffer is full or when the power stages have been shut down due to a fault.
This command can be used at any time to check the status of the chip.
• Command 2 is the first out of three special function commands. It is used to reset the
internal fault memory. Once a fault is detected by the internal diagnosis stage, it is stored in
the fault memory (i.e., the status register) and the power stages are shut down to protect
them from damage. In order to enable the chip again, this command has to be sent to the IC.
• Command 3 can be used to stop the LF data transmission immediately. Regularly, the
modulator stage works as long as new (i.e., unsent) LF data is in the data buffer. When using
this command, all data in the buffer will be deleted and the antenna driver stage is switched
to idle mode.
• Command 4 has to be used to shut down the IC. In order to start the power-down sequence
properly, no further command must be transmitted to the chip and the chip-select line (S_CS)
has to be disabled afterwards.
• Command 5 is used to write configuration data into register 1, which is used for LF data
modulation control. All register access commands are of a 16-bit structure (i.e., two data
words). The first data word defines the access itself (i.e., read or write, and the register
number). The second data word is the configuration data, which is to be sent to the ATA5278.
Note that in return for the second data word, the first input data word is sent back to the
controller. This can be used to validate the SPI transmission. Register 1 contains the four-bit-
wide antenna coil current selector (IC3..IC0) and the modulation type selector bit
(NASK_PSK). For further details, please refer to the section “Current Adjustment” on page
19.
• Command 6 can be used to validate a change in register 1 (i.e., a prior command 5
operation) or to check its actual state after a power-down period. Like all register access
commands, it consists of two data words. The return data in the second data word has the
same bit sequence as in command 5.
• Command 7 writes configuration data to register 2, which handles timing relevant setup
information. Like all register access commands, it consists of two data words, where the
second one is the configuration data itself. Note that in return for the second data word, the
first input data word is sent back to the controller. This can be used to validate the SPI
transmission. Register 2 contains the two-bit-wide LF data baud-rate selector (BR1..BR0)
and the pin CLKO prescaler bit. For further details, please refer to the sections “LF Data
Modulation” on page 13 and “Clock Supply”.
• Command 8 can be used to validate a change of register 2 (i.e., a prior command 7
operation) or to check its actual state after a power-down period. Like all register access
commands, it consists of two data words. The return data in the second data word has the
same bit sequence as in command 7.
4832C–RKE–02/06
11
11 Page | ||
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| PDF Descargar | [ Datasheet ATA5278.PDF ] | |
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