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PDF ATA5743 Data sheet ( Hoja de datos )
| Número de pieza | ATA5743 | |
| Descripción | UHF ASK/FSK Receiver | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Two Different IF Receiving Bandwidth Versions are Available (BIF = 300 kHz or 600 kHz)
• 5V to 20V Automotive-Compatible Data Interface
• IC Condition Indicator, Sleep or Active Mode
• Data Clock Available for Manchester- and Bi-phase-coded Signals
• Fully Integrated VCO
• Supply Voltage 4.5V to 5.5V, Operating Temperature Range -40°C to +105°C
• Single-ended RF Input for Easy Adaptation to λ/4 Antenna or Printed Antenna on PCB
• ESD Protection According to MIL-STD. 883 (2KV HBM)
• High Image Frequency Suppression Due to 1 MHz IF in Conjunction with a SAW
Front-end Filter; Up to 40 dB is Achievable with State-of-the-art SAWs
• Communication to Microcontroller Possible Via a Single, Bi-directional Data Line
• Power Management (Polling) is also Possible by Means of a Separate Pin Via the
Microcontroller
• Programmable Digital Noise Suppression
• SSO20 Package
UHF ASK/FSK
Receiver
ATA5743
Benefits
• Low Power Consumption Due to Configurable Self Polling with a
Programmable Time frame Check
• High Sensitivity, Especially at Low Data Rates
• Minimal External Circuitry Requirements, no RF Components on the PC Board Except
Matching to the Receiver Antenna
• Sensitivity Reduction Possible Even While Receiving
•www.DataSheet4LUo.cowm -cost Solution Due to High Integration Level
1. Description
The ATA5743 is a multi-chip PLL receiver device supplied in an SSO20 package. It
has been especially developed for the demands of RF low-cost data transmission sys-
tems with data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The
receiver is well suited to operate with Atmel's PLL RF transmitter U2741B. Its main
applications are in the areas of telemetering, security technology, and keyless-entry
systems. It can be used in the frequency receiving range of f0 = 300 MHz to 450 MHz
for ASK or FSK data transmission. All the statements made below refer to
433.92 MHz and 315 MHz applications.
Rev. 4839B–RKE–08/05
1 page  
ATA5743
4. RF Front-end
The RF front-end of the receiver is a heterodyne configuration that converts the input signal into
a 1 MHz IF signal. As seen in Figure 3-2 on page 4, the front-end consists of an LNA (Low-Noise
Amplifier), an LO (Local Oscillator), a mixer, and an RF amplifier.
The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal
oscillator) generates the reference frequency fXTO. The VCO (voltage-controlled oscillator) gen-
erates the drive voltage frequency fLO for the mixer. fLO is dependent on the voltage at pin LF,
and is then divided by 64. The divided frequency is compared to fXTO by the phase frequency
detector. The current output of the phase frequency detector is connected to a passive loop filter
and thereby generates the control voltage VLF for the VCO. By means of that configuration, VLF
is controlled in a way that fLO/64 is equal to fXTO. If fLO is determined, fXTO can be calculated using
the following formula: fXTO = fLO/64.
The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal. As
demonstrated in Figure 4-1, the crystal should be connected to GND via a capacitor CL. The
value of that capacitor is recommended by the crystal supplier. The value of CL should be opti-
mized for the individual board layout to achieve the exact value of fXTO and hereby of fLO. When
designing the system in terms of receiving bandwidth, the accuracy of the crystal and the XTO
must be considered.
Figure 4-1. PLL Peripherals
DVCC
VS
XTO
CL
LFGND
LF
R1 = 820 Ω
C9 = 4.7 nF
C10 = 1 nF
VS
LFVCC
R1 C10
C9
4839B–RKE–08/05
The passive loop filter connected to pin LF is designed for a loop bandwidth of BLoop = 100 kHz.
This value for BLoop exhibits the best possible noise performance of the LO. Figure 4-1 shows
the appropriate loop filter components to achieve the desired loop bandwidth. If the filter compo-
nents are changed for any reason, please note that the maximum capacitive load at pin LF is
limited. If the capacitive load is exceeded, a bit check may no longer be possible since fLO can-
not settle in time before the bit check starts to evaluate the incoming data stream. Self polling
will also not work in that case.
fLO is determined by the RF input frequency fRF and the IF frequency fIF using the following for-
mula: fLO = fRF - fIF
To determine fLO, the construction of the IF filter must be considered at this point. The nominal IF
frequency is fIF = 1 MHz. To achieve a good accuracy of the filter’s corner frequencies, the filter
is tuned by the crystal frequency fXTO. This means that there is a fixed relation between fIF and
fLO. This relation is dependent on the logic level at pin MODE.
5
5 Page 
ATA5743
6.1 Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry and the analog filtering is derived from one clock. As
seen in Figure 6-1, this clock cycle TClk is derived from the crystal oscillator (XTO) in combina-
tion with a divider. The division factor is controlled by the logical state at pin MODE. As
described in section “RF Front-end” on page 5, the frequency of the crystal oscillator (fXTO) is
defined by the RF input signal (fRFin) which also defines the operating frequency of the local
oscillator (fLO).
Figure 6-1. Generation of the Basic Clock Cycle
TCLK
Divider
:14/:10
fXTO
XTO
MODE
16
L : USA(:10)
H: Europe(:14)
DVCC
15
XTO
14
Pin MODE can now be set in accordance with the desired clock cycle TClk, which controls the
following application relevant parameters:
• Timing of the polling circuit including bit check
• Timing of the analog and digital signal processing
• Timing of the register programming
• Frequency of the reset marker
• IF filter center frequency (fIF0)
Most applications are dominated by two transmission frequencies: fSend = 315 MHz is mainly
used in the USA, fSend = 433.92 MHz in Europe. In order to ease the usage of all TClk-dependent
parameters on these electrical characteristics, here are displayed the three conditions for each
parameter.
• Application USA (fXTO = 4.90625 MHz, MODE = L, TClk = 2.0383 µs)
• Application Europe (fXTO = 6.76438 MHz, MODE = H, TClk = 2.0697 µs)
• Other applications (TClk is dependent on fXTO and on the logical state of pin MODE. The
electrical characteristic is given as a function of TClk).
The clock cycle of some function blocks depends on the selected baud-rate range (BR_Range)
which is defined in the OPMODE register. This clock cycle TXClk is defined by the following for-
mulas for further reference:
BR_Range =
BR_Range0:
BR_Range1:
BR_Range2:
BR_Range3:
TXClk = 8 × TClk
TXClk = 4 × TClk
TXClk = 2 × TClk
TXClk = 1 × TClk
4839B–RKE–08/05
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ATA5743.PDF ] | |
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