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PDF ATA5761 Data sheet ( Hoja de datos )
| Número de pieza | ATA5761 | |
| Descripción | (ATA5760 / ATA5761) UHF ASK/FSK Receiver | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Two Different IF Receiving Bandwidth Versions Are Available
(BIF = 300 kHz or 600 kHz)
• Frequency Receiving Range of
f0 = 868 MHz to 870 MHz or f0 = 902 MHz to 928 MHz
• 30 dB Image Rejection
• Receiving Bandwidth BIF = 600 kHz for Low Cost 90-ppm Crystals and BIF = 300 kHz for
55 ppm Crystals
• Fully Integrated LC-VCO and PLL Loop Filter
• Very High Sensitivity with Power Matched LNA
• High System IIP3 (–16 dBm), System 1-dB Compression Point (–25 dBm)
• High Large-signal Capability at GSM Band
(Blocking –30 dBm at +20 MHz, IIP3 = –12 dBm at +20 MHz)
• 5V to 20V Automotive Compatible Data Interface
• Data Clock Available for Manchester- and Bi-phase-coded Signals
• Programmable Digital Noise Suppression
• Low Power Consumption Due to Configurable Polling
• Temperature Range –40°C to +105°C
• ESD Protection 2 kV HBM, All Pins
• Communication to Microcontroller Possible Via a Single Bi-directional Data Line
• Low-cost Solution Due to High Integration Level with Minimum External Circuitry
Requirements
UHF ASK/FSK
Receiver
ATA5760
ATA5761
1. Description
www.DataSheet4U.com
The ATA5760/ATA5761 is a multi-chip PLL receiver device supplied in an SO20 pack-
age. It has been especially developed for the demands of RF low-cost data
transmission systems with data rates from 1 kBaud to 10 kBaud in Manchester or
Bi-phase code. The receiver is well suited to operate with the Atmel’s PLL RF trans-
mitter T5750. Its main applications are in the areas of telemetering, security
technology and keyless-entry systems. It can be used in the frequency receiving
range of f0 = 868 MHz to 870 MHz or f0 = 902 MHz to 928 MHz for ASK or FSK data
transmission. All the statements made below refer to 868.3 MHz and 915.0 MHz
applications.
Figure 1-1. System Block Diagram
UHF ASK/FSK
Remote control transmitter
T5750
UHF ASK/FSK
Remote control receiver
ATA5760/
ATA5761 Demod.
Control
XTO
PLL
VCO
Antenna Antenna
IF Amp
PLL
XTO
1...5
µC
Power
amp.
LNA
VCO
4896C–RKE–04/06
1 page  
ATA5760/ATA5761
The nominal frequency fLO is determined by the RF input frequency fRF and the IF frequency fIF
using the following formula (low side injection):
fLO = fRF - fIF
To determine fLO, the construction of the IF filter must be considered at this point. The nominal IF
frequency is fIF = 950 kHz. To achieve a good accuracy of the filter corner frequencies, the filter
is tuned by the crystal frequency fXTO. This means that there is a fixed relation between fIF and
fLO.
fIF = fLO/915 for BIF = 600 kHz
fIF = fLO/878 for BIF = 300 kHz
The relation is designed to achieve the nominal IF frequency of
fIF = 950 kHz for the 868.3 MHz and BIF = 600 kHz version,
fIF = 989 kHz for the 868.3 MHz and BIF = 300 kHz version and
for the 915 MHz version an IF frequency of fIF = 1.0 MHz results.
The RF input either from an antenna or from an RF generator must be transformed to the RF
input pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The
parasitic board inductances and capacitances influence the input matching. The RF receiver
ATA5760/ATA5761 exhibits its highest sensitivity if the LNA is power matched. This makes the
matching to an SAW filter as well as to 50Ω or an antenna easier.
Figure 14-1 on page 30 shows a typical input matching network for fRF = 868.3 MHz to 50Ω. Fig-
ure 14-2 on page 30 illustrates an according input matching for 868.3 MHz to an SAW. The input
matching network shown in Figure 14-1 on page 30 is the reference network for the parameters
given in the electrical characteristics.
4896C–RKE–04/06
5
5 Page 
Figure 8-1. Polling Mode Flow Chart
ATA5760/ATA5761
Sleep mode:
All circuits for signal processing are
disabled. Only XTO and Polling logic is
enabled.
Output level on Pin IC_ACTIVE => low
IS = ISoff
TSleep = Sleep x XSleep x 1024 x TClk
Start-up mode:
The signal processing circuits are
enabled. After the start-up time (TStartup)
all circuits are in stable
condition and ready to receive.
Output level on Pin IC_ACTIVE => high
IS = ISon
TStartup
Bit-check mode:
The incomming data stream is
analyzed. If the timing indicates a valid
transmitter signal, the receiver is set to
receiving mode. Otherwise it is set to
Sleep mode.
Output level on Pin IC_ACTIVE => high
IS = ISon
TBit-check
Bit check
NO OK ?
YES
Receiving mode:
The receiver is turned on permanently
and passes the data stream to the
connected microcontroller.
It can be set to Sleep mode through an
OFF command via Pin DATA or
POLLING/_ON.
Output level on Pin IC_ACTIVE => high
IS = ISon
OFF command
Sleep:
XSleep:
TClk:
TStartup:
5-bit word defined by Sleep0 to
Sleep4 in OPMODE register
Extension factor defined by
XSleepStd
according to Table 9
Basic clock cycle defined by fXTO
and Pin MODE
Is defined by the selected baud rate
range and TClk. The baud-rate range
is defined by Baud0 and Baud1 in
the OPMODE register.
TBit-check : Depends on the result of the bit check
If the bit check is ok, TBit-check
depends on the number of bits to be
checked (NBit-check) and on the
utilized data rate.
If the bit check fails, the average
time period for that check depends
on the selected baud-rate range and
on TClk. The baud-rate range is
defined by Baud0 and Baud1 in the
OPMODE register.
Figure 8-2. Timing Diagram for Complete Successful Bit Check
(Number of checked Bits: 3)
Bit check ok
IC_ACTIVE
Bit check
Dem_out
Data_out (DATA)
TStart-up
Start-up mode
1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit
TBit-check
Bit-check mode
Receiving mode
4896C–RKE–04/06
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ATA5761.PDF ] | |
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