PDF AT32UC3A0512 Data sheet ( Hoja de datos )

Número de pieza	AT32UC3A0512
Descripción	32-Bit Atmel AVR Microcontroller
Fabricantes	ATMEL Corporation
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Features • High Performance, Low Power 32-Bit Atmel® AVR® Microcontroller – Compact Single-cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation – Performing 1.49 DMIPS / MHz Up to 91 DMIPS Running at 66 MHz from Flash (1 Wait-State) Up to 49 DMIPS Running at 33MHz from Flash (0 Wait-State) – Memory Protection Unit • Multi-hierarchy Bus System – High-Performance Data Transfers on Separate Buses for Increased Performance – 15 Peripheral DMA Channels Improves Speed for Peripheral Communication • Internal High-Speed Flash – 512K Bytes, 256K Bytes, 128K Bytes Versions – Single Cycle Access up to 33 MHz – Prefetch Buffer Optimizing Instruction Execution at Maximum Speed – 4ms Page Programming Time and 8ms Full-Chip Erase Time – 100,000 Write Cycles, 15-year Data Retention Capability – Flash Security Locks and User Defined Configuration Area • Internal High-Speed SRAM, Single-Cycle Access at Full Speed – 64K Bytes (512KB and 256KB Flash), 32K Bytes (128KB Flash) • External Memory Interface on AT32UC3A0 Derivatives – SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses) • Interrupt Controller – Autovectored Low Latency Interrupt Service with Programmable Priority • System Functions – Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator – Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL) allowing Independant CPU Frequency from USB Frequency – Watchdog Timer, Real-Time Clock Timer • Universal Serial Bus (USB) – Device 2.0 Full Speed and On-The-Go (OTG) Low Speed and Full Speed – Flexible End-Point Configuration and Management with Dedicated DMA Channels – On-chip Transceivers Including Pull-Ups • Ethernet MAC 10/100 Mbps interface – 802.3 Ethernet Media Access Controller – Supports Media Independent Interface (MII) and Reduced MII (RMII) • One Three-Channel 16-bit Timer/Counter (TC) – Three External Clock Inputs, PWM, Capture and Various Counting Capabilities • One 7-Channel 16-bit Pulse Width Modulation Controller (PWM) • Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART) – Independant Baudrate Generator, Support for SPI, IrDA and ISO7816 interfaces – Support for Hardware Handshaking, RS485 Interfaces and Modem Line • Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals • One Synchronous Serial Protocol Controller – Supports I2S and Generic Frame-Based Protocols • One Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible • One 8-channel 10-bit Analog-To-Digital Converter • 16-bit Stereo Audio Bitstream – Sample Rate Up to 50 KHz 32-Bit Atmel AVR Microcontroller AT32UC3A0512 AT32UC3A0256 AT32UC3A0128 AT32UC3A1512 AT32UC3A1256 AT32UC3A1128 32058K- AVR32-01/12 1 page AT32UC3A 4. Blockdiagram Figure 4-1. Blockdiagram VBUS D+ D- TCK TDO TDI TMS JTAG INTERFACE MCKO MDO[5..0] M S E O [1 ..0 ] EVTI_N EVTO_N ID VBOF COL, CRS, R X D [3 ..0 ], RX_CLK, RX_DV, RX_ER MDC, TXD[3..0], TX_CLK, TX_EN, TX_ER, SPEED MDIO USB INTERFACE DMA DMA ETHERNET MAC PA PB PC E X T IN T[7 ..0 ] PX KPS[7..0] NMI_N NEXUS CLASS 2+ OCD UC CPU MEMORY PROTECTION UNIT INSTR DATA INTERFACE INTERFACE LOCAL BUS INTERFACE 64 KB SRAM FAST GPIO SM M M MM HIGH SPEED BUS MATRIX S S S S SM C O N FIG U R A T IO N REGISTERS BUS PB HS H SBB-PB BRIDGE B HSB HSB-PB BRIDGE A PB PERIPHERAL DMA CONTROLLER INTERRUPT CONTROLLER EXTERNAL INTERRUPT CONTROLLER REAL TIME COUNTER WATCHDOG TIM E R USART1 USART0 USART2 USART3 SERIAL PERIPHERAL INTERFACE 0/1 512 KB FLASH D A T A [1 5 ..0 ] ADDR[23..0] NCS[3..0] NRD N W A IT NWE0 NWE1 NWE3 RAS CAS SDA10 SDCK SDCKE SDCS0 SDWE RXD TXD CLK RTS, CTS DSR, DTR, DCD, RI RXD TXD CLK RTS, CTS SCK MISO, MOSI NPCS0 NPCS[3..1] RESET_N 115 kHz RCOSC XIN32 32 KHz XOUT32 OSC XIN0 XOUT0 OSC0 XIN1 XOUT1 OSC1 PLL0 PLL1 G C L K [3 ..0 ] A[2..0] B[2..0] CLK[2..0] POWER MANAGER CLOCK GENERATOR CLOCK CONTROLLER SLEEP CONTROLLER RESET CONTROLLER T IM E R /C O U N T E R SYNCHRONOUS SERIAL CONTROLLER T W O -W IR E INTERFACE TX_CLOCK, TX_FRAME_SYNC TX_DATA RX_CLOCK, RX_FRAME_SYNC RX_DATA SCL SDA PULSE WIDTH M O D U L A T IO N CONTROLLER ANALOG TO D IG IT A L CONVERTER AUDIO BITSTREAM DAC PW M[6..0] AD[7..0] D A T A [1 ..0 ] DATAN[1..0] PA PB PC PX ADVREF 32058K AVR32-01/12 5 5 Page AT32UC3A Table 5-1. Signal Description List Signal Name Function Type Active Level Comments RX_DATA SSC Receive Data Input RX_FRAME_SYNC SSC Receive Frame Sync I/O TX_CLOCK SSC Transmit Clock I/O TX_DATA SSC Transmit Data Output TX_FRAME_SYNC SSC Transmit Frame Sync I/O Timer/Counter - TIMER A0 Channel 0 Line A I/O A1 Channel 1 Line A I/O A2 Channel 2 Line A I/O B0 Channel 0 Line B I/O B1 Channel 1 Line B I/O B2 Channel 2 Line B I/O CLK0 Channel 0 External Clock Input Input CLK1 Channel 1 External Clock Input Input CLK2 Channel 2 External Clock Input Input Two-wire Interface - TWI SCL Serial Clock I/O SDA Serial Data I/O Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3 CLK Clock I/O CTS Clear To Send Input DCD Data Carrier Detect Only USART1 DSR Data Set Ready Only USART1 DTR Data Terminal Ready Only USART1 RI Ring Indicator Only USART1 RTS Request To Send Output RXD Receive Data Input TXD Transmit Data Output 32058K AVR32-01/12 11 11 Page

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