PDF STA304A Data sheet ( Hoja de datos )

Número de pieza	STA304A
Descripción	DIGITAL AUDIO PROCESSOR
Fabricantes	STMicroelectronics
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STA304A DIGITAL AUDIO PROCESSOR WITH MULTICHANNEL DDX™ STA304AEND TO END DIGITAL AUDIO INTEGRATED SOLUTION · DSP Functions: - DIGITAL VOLUME CONTROL - SOFT MUTE - BASS and TREBLE - PARAMETRIC EQ PER CHANNEL - BASS MANAGEMENT FOR SUBWOOFER - AUTO MUTE ON ZERO INPUT DETECTION 4+1 DIRECT DIGITAL AMPLIFICATION (DDX™) OUTPUT CHANNELs 6 CHANNELs PROGRAMMABLE SERIAL OUTPUT INTERFACE (by default I2S) 4 CHANNELs PROGRAMMABLE SERIAL INPUT INTERFACE (by default I2S) STEREO S/PDIF INPUT INTERFACE Intel AC'97 LINK (rev. 2.1) INPUT INTERFACE FOR AUDIO AND CONTROL ON CHIP AUTOMATIC INPUT SAMPLING FREQUENCY DETECTION 100 dB SNR SAMPLE RATE CONVERTER (1KHz SINUSOIDAL INPUT) I2C CONTROL BUS - LOW POWER 3.3V CMOS TECHNOLOGY )BLOCK DIAGRAM t(sSA SCL SDA 11 10 9 ucLRCKI/ SYNC dBICKI / BIT_CL 3 4 roSDI_1 / SDATA_OUT 1 SDI_2 / SDATA_IN 2 PRXP 18 bsolete RXN 19 I2S S/PDIF I2C SRC AC`97 TQFP44 ORDERING NUMBER: STA304A t(s) EMBEDDED PLL FOR INTERNAL CLOCK cGENERATION (1024x48 kHz = 49.152 MHz) u 6.144 MHz EXTERNAL INPUT CLOCK OR dBUILT-IN INDUSTRY STANDARD XTAL roOSCILLATOR VARIABLE DIGITAL GAIN UP TO 24dB P(0.75dB STEP) te1.0 DESCRIPTION leThe STA304A Digital Audio Processor is a single ochip device implementing end to end digital solution sfor audio application. In conjunction with STA500 bpower bridge it gives the full digital DSP-to-power Ohigh quality chain with no need for audio Digital-to- Analog converters between DSP and power stage. ROM DSP RAM DDX I2S 29 LEFT_A 30 LEFT_B 27 RIGHT_A 28 RIGHT_B 33 SLEFT_A 34 SLEFT_B 23 SRIGHT_A 24 SRIGHT_B 21 LFE_A 22 LFE_B 43 LRCKO 43 BICKO 43 SDO_1 43 SDO_2 43 SDO_3 RESET 7 PLL PowerDown 35 EAPD April 2010 14 15 XTI XTO 43 CKOUT 44 PWDN 1/31 1 page STA304A ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VDD Power Supply -0.3 to 4 V Vi Voltage on input pins -0.3 to VDD+0.3 V Vo Voltage on output pins -0.3 to VDD+0.3 V Tstg Storage Temperature -40 to +150 °C Top Operative ambient temperature -20 to +85 °C PDD Power Consumption Digital tbd mW PDA Power Consumption Analog tbd mW uct(s)THERMAL DATA dSymbol Parameter roRthj-amb Thermal resistance Junction to Ambient Value 85 Unit °C/W solete PELECTRICAL CHARACTERISTCS (VDD = 3.3V ± 0.3V; Tamb = 0 to 70 °C; unless otherwise specified) bDC OPERATING CONDITIONS OSymbol Parameter Value ) -VDD Power Supply Voltage 3.0 to 3.6V t(sTj Operating Junction Temperature -20 to 125 °C ducGENERAL INTERFACE ELECTRICAL CHARACTERISTICS roSymbol Parameter Test Condition Min. Typ. Max. Unit Note PIil Low Level Input Current Without Vi = 0V pull-up device -10 10 µA 1 teIih High Level Input Current le Without pull-up device Vi = VDD = 3.6V -10 10 µA 1 o Vesd Electrostatic Protection Leakage < 1µA 2000 V2 bs Note 1: The leakage currents are generally very small, < 1na. The value given here is a maximum that can occur after an electrostatic stress on the pin. Note 2: Human Body Model 5/31 5 Page STA304A 6.0 DAP INPUT STAGE The device provides 3 mutually exclusive input interfaces: I2S, S/PDIF and AC`97. Hereby is a small description of the characteristics for each of them and a table showing how to select it. Figure 6. I2S_SPDIF_Sel I2C I2S LRCK S/PDIF SRC SRC_Bypass DDX YRAM YRAM te Product(s)AC97 AC97_Sel PLL_Factor PLL PLL_Bypass XTI LEFT RIGHT SL/CENTER SR CENTER LFE DSP LEFT RIGHT SL/CENTER SR CENTER LFE MCK /1024 LRCK /2 or /8 CK_OUT I2S ole6.1 Input from I2S bsUsing this input interface a maximum of 4 channels can be sent to the DSP. As detailed in the related paragraph this I/F can be configured both as master or slave. When in master the sampling frequency is fixed to 48 KHz Oand the SRC can be bypassed using the SRC_Bypass configuration bit (in CRA register). If slave operation is -selected the full range between 32KHz and 96KHz is supported but the SRC must always be in the processing )path (no bypass). In order to select this interface the AC97_MODE pin must be tied to GND and the t(sI2S_SPDIF_Sel bit must be 0. c6.2 Input from S/PDIF uThis interface is compliant with the AES/EBU IEC 958, S/PDIF and EIAJ CP-340/1201 professional and con- dsumer standards. The full range from 32 KHz up to 96 KHz is supported but the SRC bypass option must be roswitched off. Using the SPDIF_Mode bit this interface can be configured as digital or analog input. If the analog mode is selected the line receiver can decode differential as well as single ended inputs. The receiver consists Pof a differential input Schmitt Trigger comparator with 50 mV of hysteresis, which prevents noisy signals from tecorrupting the data recovered. The minimum input differential voltage is 200 mV. If the digital mode is selected only the single ended operation is supported; the input signal should be CMOS lecompliant. oIn order to select this interface the AC97_MODE pin must be tied to GND and the I2S_SPDIF_Sel must be 1. bs 6.3 Input from AC`97 In order to select this interface the AC97_MODE pin must be tied to VDD (I2S_SPDIF_Sel bit ‘is don’t care). The AC`97 interface can be configured either as primary or secondary device using the external configuration pin SA. This interface support 4 sampling frequencies, according to the Variable and Double Rate Audio Codec `97 11/31 11 Page

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