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PDF 34716 Data sheet ( Hoja de datos )
| Número de pieza | 34716 | |
| Descripción | Dual Switch-Mode DDR Power Supply | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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Freescale Semiconductor
Advance Information
Document Number: MC34716
Rev. 3.0, 5/2007
1.0 MHz Dual Switch-Mode DDR
Power Supply
34716
The 34716 is a highly integrated, space-efficient, low cost, dual
synchronous buck switching regulator with integrated N-channel
power MOSFETs. It is a high performance point-of-load (PoL) power
supply with its second output having the ability to track an external
reference voltage. it provides a full power supply solution for Double-
Data-Rate (DDR) Memories.
Channel one provides a source only 5.0 A drive capability, while
channel two can sink and source up to 3.0 A. Both channels are highly
efficient with tight output regulation. With its high current drive
capability, channel one can be used to supply the VDDQ to the
memory chipset. The second channel’s ability to track a reference
voltage makes it ideal to provide the termination voltage (VTT) for
modern data buses. The 34716 also provides a buffered output
reference voltage (VREFOUT) to the memory chipset
The 34716 offers the designer the flexibility of many control,
supervisory, and protection functions to allow for easy implementation
of complex designs. It is housed in a Pb-Free, thermally enhanced,
and space efficient 26-Pin Exposed Pad QFN.
Features
• 50 mΩ Integrated N-Channel Power MOSFETs
• Input Voltage Operating Range from 3.0 V to 6.0 V
• ±1 % Accurate Output Voltages, Ranging from 0.7 V to 3.6 V
• The second output Tracks 1/2 an External Reference Voltage
www.DataSheet4U.com
• ±1 % Accurate Buffered Reference Output Voltage
• Programmable Switching Frequency Range from 200 kHz to
1.0 MHz
• Programmable Soft Start Timing for Channel One
• Over Current Limit and Short Circuit Protection on Both Channels
• Thermal Shutdown
• Output Overvoltage and Undervoltage Detection
• Active Low Power Good Output Signal
• Active Low Standby and Shutdown Inputs
• Pb-Free Packaging Designated by Suffix Code EP.
DUAL SWITCH-MODE DDR POWER
SUPPLY
EP SUFFIX
98ASA10728D
26-PIN QFN
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC34716EP/R2
-40 to 85°C
26 QFN
3.0V to 6.0V VIN
VDDQ
34716
VIN
PVIN1
BOOT1
SW1
VOUT1
PVIN2
VREFIN
BOOT2
SW2
VOUT2
INV1 INV2
COMP1
PGND1
VDDI
COMP2
VREFOUT
PGND2
VDDQ
VTT
VDDQ
Termination
Resistors
DDR Memory
Chipset
Memory Bus
VIN VREF
DDR Memory
Controller
FREQ
ILIM1
GND
PG
STBY
SD
MCU
Figure 1. 34716 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
1 page  
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Input Supply Voltage (VIN) Pin
High-Side MOSFET Drain Voltage (PVIN1, PVIN2) Pins
Switching Node (SW1, SW2) Pins
BOOT1, BOOT2 Pins (Referenced to SW1, SW2 Pins Respectively)
PG, VOUT1, VOUT2, SD, and STBY Pins
VDDI, FREQ, ILIM1, INV1, INV2, COMP1, COMP2, VREFIN, and VREFOUT
Pins
Channel 1 Continuous Output Current (1)
Channel 2 Continuous Output Current (1)
ESD Voltage (2)
Human Body Model (3)
Charge Device Model
VIN
PVIN
VSW
VBOOT - VSW
-
-
IOUT1
IOUT2
VESD1
VESD3
-0.3 to 7.0
-0.3 to 7.0
-0.3 to 7.5
-0.3 to 7.5
-0.3 to 7.0
-0.3 to 3.0
+5.0
±3.0
±2000
±750
V
V
V
V
V
V
A
A
V
THERMAL RATINGS
Operating Ambient Temperature (4)
Storage Temperature
Peak Package Reflow Temperature During Reflow (5), (6)
TA
TSTG
TPPRT
-40 to 85
-65 to +150
Note 6
°C
°C
°C
Maximum Junction Temperature
Power Dissipation (TA = 85 °C) (7)
TJ(MAX)
PD
+150
2.03
°C
W
Notes
1. Continuous output current capability so long as TJ is ≤ TJ(MAX).
2. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω) and the Charge Device
Model (CDM).
3. SW1 pin complies with ±1000V Human Body Model.
4. The limiting factor is junction temperature, taking into account power dissipation, thermal resistance, and heatsinking.
5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
6. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
7. Maximum power dissipation at indicated ambient temperature.
Analog Integrated Circuit Device Data
Freescale Semiconductor
34716
5
5 Page 
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
In modern microprocessor/memory applications, address
commands and control lines require system level termination
to a voltage (VTT) equal to 1/2 the memory supply voltage
(VDDQ). Having the termination voltage at midpoint, the power
supply insures symmetry for switching times. Also, a
reference voltage (VREF) that is free of any noise or voltage
variations is needed for the DDR SDRAM input receiver,
VREF is also equal to 1/2 VDDQ. Varying the VREF voltage will
effect the setup and hold time of the memory. To comply with
DDR requirements and to obtain best performance, VTT and
VREF need to be tightly regulated to track 1/2 VDDQ across
voltage, temperature, and noise margins. VTT should track
any variations in the DC VREF value (VTT = VREF +/- 40 mV),
(See Figure 4) for a DDR system level diagram.
The 34716 supplies the VDDQ, VTT and a buffered VREF
output. To ensure compliance with DDR specifications, the
VDDQ line is applied to the VREFIN pin and divided by 2
internally through a precision resistor divider. This internal
voltage is then used as the reference voltage for the VTT
output. The same internal voltage is also buffered to give the
VREF voltage at the VREFOUT pin for the application to use
without the need for an external resistor divider. The 34716
provides the tight voltage regulation and power sequencing/
tracking required along with handling the DDR peak transient
current requirements. It gives the user a complete DDR
power supply solution with optimum performance. Buffering
the VREF output helps its immunity against noise and load
changes.
The 34716 utilizes a voltage mode synchronous buck
switching converter topology with integrated low RDS(ON)
(50 mΩ) N-channel power MOSFETs to provide an output
voltage with an accuracy of less than ±2.0 % output voltage.
It has a programmable switching frequency that allows for
flexibility and optimization over the operating conditions and
can operate at up to 1.0 MHz to significantly reduce the
external components size and cost. The 34716 can supply up
to 5.0 A from one output and sink and source up to 3.0 A of
continuous current from the other output. It provides
protection against output overcurrent, overvoltage,
undervoltage, and overtemperature conditions. It also
protects the system from short circuit events. It incorporates
a power good output signal to alert the host when a fault
occurs.
For boards that support the Suspend-To-RAM (S3) and
the Suspend-To-Disk (S5) states, the 34716 offers the STBY
and the SD pins respectively. Pulling any of these pins low,
puts the IC in the corresponding state.
By integrating the control/supervisory circuitry along with
the Power MOSFET switches for the buck converter into a
space-efficient package, the 34716 offers a complete, small-
size, cost-effective, and simple solution to satisfy the needs
of DDR memory applications.
Besides DDR memory termination, the 34716 can be used
to supply termination for other active buses and graphics card
memory. It can be used in Netcom/Telecom applications like
servers. It can also be used in desktop motherboards, game
consoles, set top boxes, and high end high definition TVs.
VDDQ
VTT VDDQ
RT
RS
BUS
VREF
DDR Memory Controller
DDR Memory Input Receiver
Figure 4. DDR System Level Diagram
FUNCTIONAL PIN DESCRIPTION
BOOTSTRAP INPUT (BOOT1, BOOT2)
Bootstrap capacitor input pin. Connect a capacitor (as
discussed in Bootstrap capacitor on page 20) between this
pin and the SW pin of the respective channel to enhance the
gate of the high-side Power MOSFET during switching.
POWER INPUT VOLTAGE (PVIN1, PVIN2)
Buck converter power input voltage. This is the drain of the
buck converter high-side power MOSFET.
SWITCHING NODE (SW1, SW2)
Buck converter switching node. This pin is connected to
the output inductor.
POWER GROUND (PGND1, PGND2)
Buck converter and discharge MOSFETs power ground. It
is the source of the buck converter low-side power MOSFET.
COMPENSATION INPUT (COMP1, COMP2)
Buck converter external compensation network connects
to this pin. Use a type III compensation network.
Analog Integrated Circuit Device Data
Freescale Semiconductor
34716
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet 34716.PDF ] | |
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