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PDF 25AA1024 Data sheet ( Hoja de datos )

Número de pieza 25AA1024
Descripción 1 Mbit SPI Bus Serial EEPROM
Fabricantes Microchip Technology 
Logotipo Microchip Technology Logotipo



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25AA1024
1 Mbit SPI Bus Serial EEPROM
Device Selection Table
Part Number
25AA1024
VCC Range
1.8-5.5V
Page Size
256 Byte
Temp. Ranges
I
Packages
P, SM, MF
Features
• 20 MHz Maximum Clock Speed
• Byte and Page-level Write Operations:
- 256 byte page
- 6 ms maximum write cycle time
- No page or sector erase required
• Low-Power CMOS Technology:
- Maximum Write current: 7 mA at 5.5V
- Maximum Read current: 10 mA at 5.5V,
20 MHz
- Standby current: 1 µA at 2.5V, 85°C
(Deep Power-down)
• Electronic Signature for Device ID
• Self-Timed Erase and Write Cycles:
- Page Erase (6 ms maximum)
- Sector Erase (10 ms maximum)
- Chip Erase (10 ms maximum)
• Sector Write Protection (32K byte/sector):
- Protect none, 1/4, 1/2 or all of array
• Built-in Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• High Reliability:
- Endurance: 1M erase/write cycles
- Data Retention: >200 years
- ESD Protection: 4000V
• Temperature Ranges Supported:
- Industrial (I):-40°C to +85°C
• RoHS Compliant
Pin Function Table
Name
Function
CS
SO
WP
VSS
SI
SCK
HOLD
VCC
Chip Select Input
Serial Data Output
Write-Protect
Ground
Serial Data Input
Serial Clock Input
Hold Input
Supply Voltage
Description
The Microchip Technology Inc. 25AA1024 is a
1024 Kbit serial EEPROM memory with byte-level and
page-level serial EEPROM functions. It also features
Page, Sector and Chip erase functions typically
associated with Flash-based products. These functions
are not required for byte or page write operations. The
memory is accessed via a simple Serial Peripheral
Interface (SPI) compatible serial bus. The bus signals
required are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled by a Chip Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused,
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
The 25AA1024 is available in standard packages
including 8-lead PDIP and SOIJ, and advanced 8-lead
DFN package. All devices are RoHS compliant.
Package Types (not to scale)
CS 1
SO 2
WP 3
VSS 4
DFN
(MF)
PDIP/SOIJ
(P, SM)
8 VCC
CS 1
7 HOLD SO 2
6 SCK WP 3
8 VCC
7 HOLD
6 SCK
5 SI
VSS 4
5 SI
2007-2015 Microchip Technology Inc.
DS20001836J-page 1

1 page




25AA1024 pdf
25AA1024
TABLE 1-3: AC TEST CONDITIONS
AC Waveform
VLO = 0.2V
VHI = VCC - 0.2V
VHI = 4.0V
CL = 30 pF
(Note 1)
(Note 2)
Timing Measurement Reference Level
Input
0.5 VCC
Output
0.5 VCC
Note 1: For VCC 4.0V
2: For VCC > 4.0V
FIGURE 1-1: HOLD TIMING
CS
16
SCK
SO n + 2
n+1
17
18
n
SI
n+2
n+1
n
16 17
19
High-Impedance
Don’t Care
n
5
n
HOLD
n-1
n-1
FIGURE 1-2: SERIAL INPUT TIMING
CS
2
Mode 1,1
SCK Mode 0,0
5
6
SI MSB in
SO
7
High-Impedance
8
4
12
11
3
LSB in
2007-2015 Microchip Technology Inc.
DS20001836J-page 5

5 Page





25AA1024 arduino
25AA1024
2.3 Write Enable (WREN) and Write
Disable (WRDI)
The 25AA1024 contains a write enable latch. See
Table 2-4 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
The following is a list of conditions under which the
write enable latch will be reset:
• Power-up
WRDI instruction successfully executed
WRSR instruction successfully executed
WRITE instruction successfully executed
PE instruction successfully executed
SE instruction successfully executed
CE instruction successfully executed
FIGURE 2-4:
WRITE ENABLE SEQUENCE (WREN)
CS
SCK
01234567
SI 0 0 0 0 0 1 1 0
High-Impedance
SO
FIGURE 2-5:
WRITE DISABLE SEQUENCE (WRDI)
CS
SCK
01234567
SI 0 0 0 0 0 1 10 0
High-Impedance
SO
2007-2015 Microchip Technology Inc.
DS20001836J-page 11

11 Page







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